Re: Recent s.s.t.c work

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Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

2 Steves, Sean T. & others-

Sean, you had written about compensating for delay/phase-shift in a 
s.s.t.c. feedback loop and that got me thinking about it.  I came up 
with a scheme that seems to do the job.  Ckeck out
http://www.hot-streamer.com/temp/KCH-h-br.jpg

http://www.hot-streamer.com/temp/KCH-h-br-waves.jpg.

The feedback scheme is basically how I am doing it in my present 
hardware except for the U1 delay element.  Primary current is sensed 
in current-transformer TX2 whose output is clamped by D1-D4.  The 
resultant voltage across R7 drives the bottom end of C3, which is the 
capacitor in the Schmitt-oscillator circuit of U4.  In the hardware, 
the U4 circuit provides drive to its TX1 all the time, with 
additional circuitry prior to each of the IGBT gates that turns on 
the plus-going drives only during the spark events.  The all-the-time 
drive is for the purpose of keeping the 4 floating gate-driving power 
sources (electrolytics) charged up between sparks.  As soon as the 
primary starts developing current for a spark-event, the R7 voltage 
takes over and establishes the proper feedback frequency, differing 
from that of the U4 circuit itself.

The U4 output (in the hardware) drives amplifiers simulated by E1, 
which drive the IGBT-drive transformer like TX1 which in turn drives 
(via the additional electronics) the 4 IGBTs of the H-bridge.

There exist numerous sources of phase-shift or delay in the loop, in 
the simulation as in the hardware:  C10, R1, TX1, the IGBTs and the 
U4 circuit.  In the simulation, I embellish the IGBTs with 
gate:source and gate:drain capacitances since the simulation 
IGBT-elements don't seem to include those.

So here's the solution, seemingly:  The U1 delay-element in the 
simulation completely compensates for all those shifts and delays, as 
you can see from the -waves.jpg image.  The red sine wave is the 
primary current and the green wave is the current from power source 
V1.  Switching of the IGBTs occurs almost exactly at the 
primary-current zero-crossings, with 6.2 us of delay.

I would plan to use a shift register in the hardware (and I will make 
a new simulation shortly incorporating one, just to be sure).  A 
16-stage shift register would run from perhaps a 2.5 MHz clock, 
yielding a 400 ns delay per s-r stage for a total available delay of 
6.4 us.  One would just pick off the delay needed in a particular 
system.  Notice that the delay is a bit short of the time duration of 
1/2 cycle of the primary's Fr (short by the amount of the required 
delay).  Thus, the total phase shift around the feedback loop must 
compensate for that, by the inclusion of a 180 degree shift that 
would not be present absent the delay element.

Comments solicited from all!

 Ken Herrick