Re: Recent s.s.t.c work

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Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

I just realized that the glitch in the -9 image I referred to in my 
previous posting can't be very much due to Miller effect since no 
bridge power was applied when I took the photo.  Must be something else...

KCH

-------- Original Message --------
Subject: Re: Recent s.s.t.c work
Date: Tue, 18 Oct 2005 17:10:58 -0700
From: K. C. Herrick <mailto:kchdlh@xxxxxxx><kchdlh@xxxxxxx>
To: Tesla list <mailto:tesla@xxxxxxxxxx><tesla@xxxxxxxxxx>
References: 
<mailto:6.2.3.4.2.20051018151518.01db1750@xxxxxxxxxxxxxxxxxxxxxxx><6.2.3.4.2.20051018151518.01db1750@xxxxxxxxxxxxxxxxxxxxxxx> 



Steve Ward (& all)-

[snipped]

In -9 you can see that one of the gate voltages is still slowing down 
before the 0V level is reached.  II think that is due to Miller 
effect in the IGBT,  when the "top" IGBT on that side of the bridge 
turns off, pulling too much current, thru the gate:drain capacitance, 
from the gating transistor, which does not have enough base drive at 
that instant or has lower gain.  I'll need to work on that.

[snipped]