Re: DRSSTC eye candy (sparks)

["Tesla list" <tesla@xxxxxxxxxx>]

Original poster: Steve Ward <steve.ward@xxxxxxxxx>

Hi Ken,

It looks almost as if you built a flip flop from AND gates?  Anyway,
assuming your timing diagram is truthful, it should work just fine.

I will have to keep this schematic on my hard drive, it might be
useful later on.

Regards,

Steve Ward


On Mon, 21 Mar 2005 18:56:09 -0700, Tesla list <tesla@xxxxxxxxxx> wrote:
> Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>
>
> Steve (& all)-
>
> Thanks for the additional info--and those are super pictures!  Thinking on
> your synchronizing circuit, I came up with what seems to be a simpler one &
> would appreciate your comment.  I'll post it via
> <mailto:tfritz@xxxxxxxxxxxxxxxxxxxxxxx>tfritz@xxxxxxxxxxxxxxxxxxxxxxx as
> synchronizer-kch.jpg and sync-waves-kch.jpg.
>
> http://hot-streamer.com/temp/synchronizer-kch.jpg
>
> http://hot-streamer.com/temp/sync-waves-kch.jpg
>
> It's just one 74HC00 (I included gates U4 & U7 in the simulation just so I
> could get the waveforms to appear separated, as shown).  With V3 (U4-out)
> high, U6 is enabled.  If its output happens to start out high at turn-on,
> U1, U2 & U3 are enabled and the first high from V1 (U7-out high) will set
> the FF, via U2, for U1-out = high and U6-out = low.  U6's low-out disables
> U1, U2 & U3.
>
> When V3 goes low, U1, U2 & U3 are enabled.  V1's signal commences passing
> through U2 & U3 to produce the output; note that the first U3-out pulse's
> transition may not be synchronized with whatever signal is coming from
> V1--but that's no never-mind.  U2's output signal at U1's input will cause
> U1 to operate but that will have no effect on U6 since V3 remains
> low.  Only when V3 again goes high will the next-succeeding U1-output high
> reset the FF to disable U1, U2 & U3.  And that disabling occurs
> synchronously with V1's transition.
>
> Ken Herrick

(snip!)