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Re: DRSSTC eye candy (sparks)

Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

Steve (& all)-

Thanks for the additional info--and those are super pictures! Thinking on your synchronizing circuit, I came up with what seems to be a simpler one & would appreciate your comment. I'll post it via <mailto:tfritz@xxxxxxxxxxxxxxxxxxxxxxx>tfritz@xxxxxxxxxxxxxxxxxxxxxxx as synchronizer-kch.jpg and sync-waves-kch.jpg.



It's just one 74HC00 (I included gates U4 & U7 in the simulation just so I could get the waveforms to appear separated, as shown). With V3 (U4-out) high, U6 is enabled. If its output happens to start out high at turn-on, U1, U2 & U3 are enabled and the first high from V1 (U7-out high) will set the FF, via U2, for U1-out = high and U6-out = low. U6's low-out disables U1, U2 & U3.

When V3 goes low, U1, U2 & U3 are enabled. V1's signal commences passing through U2 & U3 to produce the output; note that the first U3-out pulse's transition may not be synchronized with whatever signal is coming from V1--but that's no never-mind. U2's output signal at U1's input will cause U1 to operate but that will have no effect on U6 since V3 remains low. Only when V3 again goes high will the next-succeeding U1-output high reset the FF to disable U1, U2 & U3. And that disabling occurs synchronously with V1's transition.

Ken Herrick

Tesla list wrote:
Original poster: Steve Ward <mailto:steve.ward@xxxxxxxxx><steve.ward@xxxxxxxxx>

First order of business:

More sweet arc pictures from my large DRSSTC run tonight (bottom of page):


Now if that doesnt get your attention, i dont know what will ;-). I think i managed to set off a car alarm as well.

Now to respond to Ken: (sorry for all the snipping)

On Fri, 18 Mar 2005 16:34:35 -0700, Tesla list <mailto:tesla@xxxxxxxxxx><tesla@xxxxxxxxxx> wrote:
> Original poster: "K. C. Herrick" <mailto:kchdlh@xxxxxxx><kchdlh@xxxxxxx>
> Steve (& all)-
> Thanks kindly for the added info. Leading to a few more queries/comments
> interspersed...
> 1. So the 1T primaries of T1 & T2 are connected in series (& in series
> with, of course, the primary ckt)?

If i understand you, yes, that is true.  Both CTs reside on the
primary conductor... the primary of the CTs IS the output wire from
the bridge.

> 2.  Why D19-D22, when 2 back-to-back zeners might do it?

I wanted to make sure that the slow recovery time of the zeners
wouldnt foul anything up.

> 3.  Have you thought to try eliminating one of T1-T4 by connecting, say,
> T4's secondary to drive T1's & T3's primaries in series?

I did try this once, but it didnt seem to work quite right, but i was
having other problems at that time as well, so it might actually be
ok.  I get these ferrite cores 5 for $1, and wire is cheap, so i dont
mind using 4 of them.

> 5.  Perhaps one should always choose the lower freq. so as to minimuze
> efficiency-loss due to the IGBTs' transition-times.

Ah yes, that was one of my reasons too, forgot to mention that.

> 6. So basically, U1's /CLR=low forces /Q high, enabling the drive while
> blocking CLK from affecting /Q. /CLR must then go high for > 1/2 CLK
> period but < 1 full period, whereupon CLK is enabled to toggle /Q low, thus
> cutting off the drive exactly @ the primary-current z.c. Do I have that
> right?


  If so, then the /CLR=high duration must be kept adjusted dependent
> on primary tuning.

If you wanted to keep the number of cycles constant, yes.  That is not
hard to do, i have a remote controller, its just a twist of a knob

  Would be nice if there were a way around that...

> 7. I'd had somewhat the same problem with my feedback-t.c., in assuring
> that oscillations would start when I gated the drive on. I solved that by
> incorporating enough linear gain in the amplifying chain so that
> noise--picked up + internal--would provide the needed impulse to get things
> going. I had to use 3 linearized CMOS inverters in series followed by 1
> digital, with the input-drive just the +/- 0.7V across a pair of
> back-to-back diodes in series with the secondary return. Couldn't employ
> all stages w/in one IC due to intra-substrate coupling; had to use 2,
> 74Cs--& not HCs.

There was no good place to inject some starting noise, so i decided to
make the circuit start up by having the gate drivers send out a pulse
when they are enabled.  This is quite realiable and seems to work

> I really like your implementation; much less complex than mine was! Your
> gate-drive xfmrs I especially like. I'd gotten part way thru building a
> variable-L 4-6T primary, to use with a spark-gap and my 12"-dia. secondary
> coils, when a good part of my motivation & energy went. I hope to get some
> back & to continue w/ that project, but perhaps trying s.s. yet once again.

Hopefully those new pics i just post will motivate you a bit as well
;-).  You can get those brick IGBTs (CM300DY-24H) on ebay for about
$30 a pop.  1 of them would easily handle sparks in the 6' range.  Im
using 2 for up to 11' now, but hope to eventually achieve 12' after i
raise the whole coil up on some bricks (to avoid ground strikes) and
to get a better spark target (something 10' tall or so).  Most of my
sparks just fly off 9' or so into the air with nothing to connect



> Ken Herrick
> [snipped]