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Re: DRSSTC eye candy (sparks)

Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

Steve (& all)-

Thanks kindly for the added info. Leading to a few more queries/comments interspersed...

Tesla list wrote:
Original poster: Steve Ward <mailto:steve.ward@xxxxxxxxx><steve.ward@xxxxxxxxx>

Hi Ken,

I will try to answer your questions below:

Firstly, see the new schematic i *just* posted after i realized i had
not updated the one on that page:

<http://www.stevehv.4hv.org/DRSSTC1/DRSSTC1OCDsch.JPG>http://www.stevehv.4hv.org/DRSSTC1/DRSSTC1OCDsch.JPG



On Thu, 17 Mar 2005 19:10:46 -0700, Tesla list <mailto:tesla@xxxxxxxxxx><tesla@xxxxxxxxxx> wrote:
> Original poster: "K. C. Herrick" <mailto:kchdlh@xxxxxxx><kchdlh@xxxxxxx>
>
> Steve (& all)-
>
> Very nice, indeed; love those sparks! I hope your work will help restore
> some of my motivation; I haven't had a running coil for a year or so, now.
>
> A few questions:
>
> 1. I take it the "1:100" c.t. is 2, 1:33 in tandem, as you mentioned
> elsewhere--right?

Actually, right now on that coil i use 4 CTs total, in pairs of 2 1:33
CTs in cascades.  So for my feedback circuit i have the output of my
bridge pass through a 33 turn CT, then the output of that CT forms a
single turn into another 33 turn CT.  This in effect gives about a
1:1000 ratio, stepping the current down by 1000.  I use this exact
same method for feedback as well as the over current detection
circuit.  The only difference is that the feedback is terminated for a
"digital" signal (hi/low) and the overcurrent detection CT is
terminiated with a resistor for an analog representation of the
current as a voltage.  Hope that is clear, it should be if you look at
the schematic.

1. So the 1T primaries of T1 & T2 are connected in series (& in series with, of course, the primary ckt)?

2.  Why D19-D22, when 2 back-to-back zeners might do it?

3. Have you thought to try eliminating one of T1-T4 by connecting, say, T4's secondary to drive T1's & T3's primaries in series?

>
> 2.  What IGBTs do you use--and would they work adequately @ 100-130
> KHz?  (My 2 secondarys are 100 & 130 or so KHz. & I wouldn't have the
> energy to make a new one.)

Im using some mini-block IGBTs made by fairchild, part number
HGT1N40N60A4D.  They are hefty little guys rated 110A.  They work just
fine at 100-130khz (i used them at 300khz in my mini coil).  In fact,
before i wound my new secondary i was using one that operated at about
130khz (this meant tuning the primary to 95khz).  I pushed them to
over 1000A pulsed at 95khz with no failure or signs of stress.  You
might want to check out the IGBTs terry is using (hopefully terry will
post the part number again, i dont remember it off hand) since you can
currently buy them.  Fairchild seems to have discontinued the
particular IGBT i use, though i still see people sell them on ebay
from time to time.
4. Terry?... 
>
> 3.  Why the disparity of 55 vs. 75 KHz, primary &
> secondary?  Expediency?  55 KHz to suit the IGBTs?

2 reasons for the drastic tuning difference.  Frequency splitting
causes there to be 2 new frequencies of preferred operation, one above
and one below the natural Fr.  In theory we could drive the coil at
the upper "pole", or at Fr, or at the lower "pole".  When tuned to Fr,
you will get a notched waveform, but tuning to the upper or lower
poles, you get a nice linear ring up in the primary and secondary
circuits (this i believe allows you to transfer energy without time
limit).  I chose the lower pole because streamer detuning will cause
the secondary to have a lower resonance.  Now i tune the coil even
LOWER than this lower pole frequency, due to streamer loading.  So
what happens is, corona forms during the first few cycles of drive,
but not enough to really pull the system into tune.  The primary
current and voltage build tremendously during this time until that
corona grows enough and the secondary frequency shifts.  Eventually
the 2 circuits are perfectly tuned (usually the last 3-4 cycles of
each "burst").  When this happens, all that built up energy in the
tank circuit gets sucked out by the secondary coil!  IF the secondary
doesnt break out (either insufficient voltage, or improper tuning)
then all the energy goes back into the filtering caps.
5. Perhaps one should always choose the lower freq. so as to minimuze efficiency-loss due to the IGBTs' transition-times. 
>
> 4.  Could you amplify on the circuits of your drawing DRSSTC Controller
> dated 12/18/04?

Oops, thats an old schematic and does not represent the circuit as it
is now!   See this new one (it is full size, should not have any
problem reading it, you may need to make your browser expand it):

<http://www.stevehv.4hv.org/DRSSTC1/DRSSTC1OCDsch.JPG>http://www.stevehv.4hv.org/DRSSTC1/DRSSTC1OCDsch.JPG 


Basically how the FF works is this.  The first interrupter pulse turns
the FF "off" making Q\ high (enabling the gate driver).  When the
interrupter goes low, the FF is active and waits for a change in the
clock, at which point Q\ goes low. That is until the next interrupter
pulse comes along several mS later to turn it back "off" (which is
really ON!).
6. So basically, U1's /CLR=low forces /Q high, enabling the drive while blocking CLK from affecting /Q. /CLR must then go high for > 1/2 CLK period but < 1 full period, whereupon CLK is enabled to toggle /Q low, thus cutting off the drive exactly @ the primary-current z.c. Do I have that right? If so, then the /CLR=high duration must be kept adjusted dependent on primary tuning. Would be nice if there were a way around that... 
Now there is a bit of an error here, and that is, what if there never
IS a clock input?  Well the FF is turned active (waiting to recieve
clock input) but it never gets it, so its never reset (the coil wont
do a thing in this case!).  What i did was send a delayed interrupter
pulse into the  set (PRE) pin so that if there never is a clock input,
the whole thing "resets" regardless.  This delayed pulse into PRE must
delayed by about 2X the length of an RF cycle so that this pulse
doesnt terminate the burst prematurely (that is, PRE changes before
the clock input changes), which would negate the benefit of the FF.
7. I'd had somewhat the same problem with my feedback-t.c., in assuring that oscillations would start when I gated the drive on. I solved that by incorporating enough linear gain in the amplifying chain so that noise--picked up + internal--would provide the needed impulse to get things going. I had to use 3 linearized CMOS inverters in series followed by 1 digital, with the input-drive just the +/- 0.7V across a pair of back-to-back diodes in series with the secondary return. Couldn't employ all stages w/in one IC due to intra-substrate coupling; had to use 2, 74Cs--& not HCs.

I really like your implementation; much less complex than mine was! Your gate-drive xfmrs I especially like. I'd gotten part way thru building a variable-L 4-6T primary, to use with a spark-gap and my 12"-dia. secondary coils, when a good part of my motivation & energy went. I hope to get some back & to continue w/ that project, but perhaps trying s.s. yet once again.

Ken Herrick

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