Re: SSTC, xfmr gate drive oddity

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "Jan Wagner by way of Terry Fritz <twftesla-at-qwest-dot-net>" <jwagner-at-cc.hut.fi>


> > now only 5V instead of 13.6V. It is till a good square wave, though. But,
> > the 1:1 transformer output is now -2.5V<->+2.5V (and this is also seen on
> > the primary side of course). Not the expected -6.8V<->+6.8V.
> 
> With output current, the gate-source voltages must be above the
> threshold voltages of the mosfets, and somewhat higher to allow for
> significant current. This may be several volts easily. 

O-oh. Mosfet datasheets say min 2V and max 4V as V_t. Yup. Now, _that_
really explains things!! Plus the C_gs => output coupling. 
I hadn't checked the datasheets (surplus mosfets, so why bother checking?
;) before and "assumed" it was just 1V. 

> > Any ideas, tips, etc, would be highly welcome!
> > That is how to get the full +-6.8V voltage swings accross the pulse
> > transformer primary? Because +-2.5V is really on the weak side.
> 
> A possibility is to interchange the mosfets. You will have then a CMOS
> inverter, that will produce almost +13.6 to 0 output with 0 to +13.6
> input.

Like in
  http://www.fairchildsemi-dot-com/ds/CD/CD4049UBC.pdf , second page?
Hmm... i'll try that one out!  :o)


Many thanks!

 - Jan

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