User-agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0
Em 28/01/2014 21:36, romsigurthr@xxxxxxxxx escreveu:
Hello Antonio,
I’ve recently begun designing a DRSSTC with similar parameters (“high” inductance primary, small capacitance tank, and limited to short burst lengths (3 cycles for current MMC, I can get to 6 by doubling voltage rating). It is my understand that the less than spectacular streamer length is due to the fact that there isn’t enough time for streamers to grow properly. At 3.3uS/cycle a 10 cycle burst is only 33uS. Going up to 20 cycles yields 66uS. Most “large output” DRSSTCs run around 120-500uS bursts and typically have primary peak currents around 400-900A. That being said, the output in your video looks quite good for only 66uS ontime.
Why just 3 cycles? Would be mode 9:11:13. Requires tight coupling
(0.35). I think that streamers grow with successive burst too, if they
are not excessively spaced. I see this in my coil, with the streamer
length increasing clearly with the burst frequency (limited to about 200
Hz currently).
The 1MHz “noise”:
You didn’t state what the timing method for the interrupter was, and as there is no evidence of poor performance or the 1MHz being an upper excitation mode in the output of the DRSSTC one has to conclude that it must be from the interrupter or radiating from parasitic oscillations in the wiring.
Some parasitic coupling in the wiring. A ferrite core around the output
cable almost eliminated it. The oscillations start after a burst, and
remain at full power until the next burst, when they sometimes stop
until the next burst. Very strange behavior.
Your coil’s output:
In order to increase spark length the burst length must be increased. Doing so you will get a higher peak primary current. Increasing Burst Length also increases the voltage across the MMC, so you’ll need to adjust for that as well. Using a higher peak current capacity switch to adjust for the longer burst length is easy; Fairchild’s FDL100N50F MOSFETs will easily tolerate 400A pulsed at low duty cycles.
I didn't measure the voltage over the primary capacitor yet, but the
simulations say that it is at safe level, at least in the no-breakout
condition, or with constant linear load. In the way I tune the system,
driving between the resonances, the input current does not grow with
burst length, above the designed ideal burst length that produces a
single beat in the current. In practice, as I have observed, It grows a
bit because the streamer loading detunes the system. One of the things
that I want to study with this coil is exactly what happens.
You can use this formula to find what your MMC voltage will be at a certain peak current.
Vmmc = (Ipk * 2 * Pi * Lpri * fres)
Rearranged to find the peak current your current MMC can support.
I = Vmmc / (2* Pi * Lpri * fres)
For a 13.5uH primary at 294KHz and a Vmmc limit of 4.8kV you can support 192.5Apk. This is of course before losses and loading, and as you noted; loading is hard to calculate.
I have the exact expressions implemented in my drsstcd program, assuming
linearity at least.
This is all a rather complicated way of saying that the next step to increasing output would be to increase your MMC’s voltage rating so you can increase your Burst Length to give streamers more time to grow, and more current to support their growth. One reason I decided to reply with all this info is that SSTCs and DRSSTCs are rarely the subject of discussion on the TCML and I hope that others may learn from the info presented here.
For awhile I have to rebuild the driver. After I managed so supress the
oscillations it stopped suddenly. An examination revealed a shorted
mosfet and the other leaking. I had installed two mosfets in parallel at
each leg of the half bridge, with one that could have the gate connected
to the gdt or to the source, so I could select using one or two mosfets.
My gdt, to be improved, was not good enough to drive two mosfets in
parallel, so I was using just one, with the other not conducting. The
last thing that I found today was that the inactive transistors were
also apparently damaged. Verifying tomorrow. The rebuild will include
some protective devices.