.. In the way I tune the system,
driving between the resonances, the input current does not grow with
burst length, above the designed ideal burst length that produces a
single beat in the current. In practice, as I have observed, It grows a
bit because the streamer loading detunes the system. One of the things
that I want to study with this coil is exactly what happens.
Running the coil as you do, i.e. the driving frequency close to the secondary
resonance, probably is the most effective way of transferring energy from the
bridge through the primary into the secondary.
Capacitive arc loading will lower the secondary fres, though, and move it away from the
driving frequency. That causes a more inefficient power transfer to the secondary.
Inefficent in the sense, that more primary current is needed to transfer the same
amount of power. The secondary will then draw less power from the primary
so that more power is fed into the primary tank than going out of it. This will cause
the primary current to rise.
Most DRSSTCs aren't run this way. Usually the primary tank is tuned quite a bit lower
than the secondary and since they often use zero current switching on the primary,
the running frequency will be about primary fres.
Since the runnig frequency is much less than the secondary fres, primary current will rise for
some time almost without beats until the arc breaks out. This will then lower secondary fres,
which moves its frequency closer to the running frequency. The power transfer to the
secondary will be enhanced, which will grow the arc and in turn lower secondary fres more.
Basically this is positive feedback loop leading to a rapid discharge of primary energy into
the secondary and then to the arc. During this surge the power delivered to the arc can be
much larger than the power the bridge supplies.
I believe it is generally preferable to use longer bursts. The power delivered by a bridge
is proportional to the primary current I, while the losses in the transistors are proportional
to I^2. So a longer burst with less current will stress the fets less than a shorter one of the
same total energy. On the other hand, an arc of longer duration will consume more energy
without necessarily getting longer.
The scheme above, though, allows to make the arc time, i.e. during the postive feedback
surge, to be made much shorter than the the burst time. This resembles the operation of
an SGTC: The primary is slowly charged up but instead of a gap triggering the arc,
the breakout of the arc triggers the discharge of the primary tank.
My idea of a "perfect DRSSTC" would be one using a large primary inductance, which
could store a lot of energy for a given max primary current and a corresponding long burst
time to charge it up. That would reduce stress on the transistors. Most of this is
unexplored territory.
Udo
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