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Re: [TCML] SSTC half bridge
In steady state, the 2 circuits behave exactly the same *assuming* there is
a capacitor from +340V to GND that is much bigger than the DC blocking cap,
and the stray inductances are small.
The difference between these 2 circuits, when functioning as intended, are
insignificant. The current through the primary coil will be the same either
way, assuming the total DC blocking capacitance is the same (Cblock for a is
2X Cblock for b). The only benefit i can see for b is that it establishes a
DC bias of 140V much faster than you would get with the leakage current of
the mosfets acting as an R-divider in case a, to charge up the DC blocker
cap to 170V. Its a subtle difference that is not likely to matter.
Ive build drivers that use either setup, no notable differences.
Steve
On Fri, Jun 4, 2010 at 12:36 AM, Herwig Roscher <herwig.roscher@xxxxxx>wrote:
>
> Hello,
>
> I am planning on building a SSTC, driven by a half bridge of
> POWERMOSFETs. Searching the archives and the web, I found two
> topologies:
>
> a. +340 V
> |
> upper FET
> |
> *------ primary coil-----
> | |
> lower FET = dc blocking capacitor
> | |
> GND GND
>
>
> b. +340 V
> |
> *----------------------------
> | |
> upper FET = dc blocking capacitor
> | |
> *------ primary coil-----*
> | |
> lower FET = dc blocking capacitor
> | |
> GND GND
>
> What are the pros and cons for these circuits? Could somebody please
> enlighten me?
>
> Regards,
>
> Herwig
>
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