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Re: Snubbing an IGBT in a sstc

Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

Steve (& all)-

As always, your comments are very cogent! The repetitive avalanche energy maximum for the IRFBE30 MOSFET is 13 mJ. My understanding is that 1 mJ is 1 mW-second, which would be 1 W-millisecond, which would be 1000 W-microsecond...is that right? So over 1 us, the IRFBE30 should accomodate an energy of 13 KW-microseconds. (Seem like a lot, for a teeny little TO-220 transistor!) And as you point out, 2 A x 800 V yields 1.6 KW which is a lot less, over that 1 us.

Am I missing something?... Does one need snubbers, as such, in an H-bridge configuration? Is not the best you can do to utilize lowest-inductance bus structuring plus capacitive bypassing of V+ and V- right at the transistors? In a single-ended or push-pull configuration such as I'm contemplating there's no reverse-diode(s) to "catch" the overshoot so snubbing is essential. But in a 1/2- or full-H, overshoot--absent stray inductance--is absorbed by the reverse diode of the "off" transistor(s). Enlighten me on this.

I've bought some used Powerex CM300DY-24H half-bridges (and also some CM300DU-24Fs) which I'm hoping to use. Nothing in the data sheets on lead-inductance, of course. But I do notice the boast, "High Frequency Operation (20-25 KHz)", so...we'll see what happens (if anything at all) at 150 KHz.

In the simulation, I got h-f oscillation also--until I added the R-C elements at the base of Q3.

There is, of course, IGBT current during the snubbing event. But, in simulation at any rate, that current diminishes to zero in 600 ns at which time the IGBT's gate voltage returns to its negative-off level. So no current-overshoot appears at that time.

In a push-pull arrangement, I think there might be harm in allowing both transistors to be on at the same time. Mutual inductance between the primary-halves would allow excess current to be drawn, limited, I think, only by the coupling coefficient and the circuit resistances and stray inductances. Is that right?

As to the active snubber acting fast enough... The rate of rise of the IGBT collector voltage at turn-off simulates at 1800 V/us with the 100 nF value of C3, the 2 uH primary-half and the 20 m-ohm circuit resistance. So I would have, in a real implementation, 1200/1800 = 2/3 us absolute max. in which to effect the snubbing. Not a whole lot of time, I agree.

...And what is an RCD snubber? Would that be what I show as the D6/C3/D1/R9 configuration? I know that's called a snubber circuit...but to me that's a misnomer: it doesn't snub, i.e. clamp, the voltage but merely slows down its rise.

I may well need to do something more with this design other than turn it into hardware & hope for the best: I simulated 2 uH of inductance in the drain lead of the avalanche-MOSFET Q1 and...sure enough--oscillation during snubbing, shooting the IGBT's collector voltage to 1.2 KV or so during some of the events. However...I question whether a real "brick" IGBT will respond that fast, i.e. support the feedback loop; the oscillation is at about 16 MHz. Do you have a thought on that? Also, in regard to reducing bus-inductances as you suggest...I wonder if that's very important in a single-ended or push-pull configuration? Any bus inductance is merely going to add to the inductance of the primary per se; the main concern is to keep the loop inductance in the snubber circuit itself to a minimum--not so?

So, best to go on to spark gaps and pole pigs instead? What's to fail there?? I even have a pole-pig--which I'd love to get rid of. But not for me, I'm afraid...I'm too old.


Tesla list wrote:
Original poster: "Steve Ward" <mailto:steve.ward@xxxxxxxxx><steve.ward@xxxxxxxxx>


Be sure not to exceed the avalanche energy rating for the MOSFET.  Its
typically in the mJ, so its not a whole lot.  1600W for 1uS is about
16mJ, so it might be OK.

I did extensive R & D on snubber design for my H-bridge drives.  I
eventually found that my snubbers just couldnt overcome the internal
package inductance of my relatively "old" IGBTs (they have some
50-60nH from each lead).  I found my voltage spikes to oscillate in
the 10Mhz region, meaning that your snubbers have to have exceedingly
small inductance to work effectively on this noise.  In the end, i
ended up leaving the snubbers off, and the coil works just fine.  But,
this was after creating an extremely low inductance buss structure
(laminated plate conductors).  I also slowed down the IGBT turn on a
little, since the voltage spikes were caused by the opposing
free-wheel doide's not-so-soft recovery.

There is something i dont understand about your snubber design.  It
has to turn the main IGBT back ON to clamp the spike.  But, the IGBT
is supposed to be off because the other IGBT is now ON.  I realize
that if this were a push-pull arrangement, driving a center-tapped
primary, then there is no real harm in having both switches ON at the
same time.  But, at some point you have to turn this IGBT OFF... so
wouldnt there still be a transient when that happens?  Otherwise, why
not just have overlapping gate drive signals?  Anyway, i think i might
be missing the essence of your design, so perhaps either i need to
spend some time and look at it myself, or maybe you can shed some more
light on things.

Finally, i worry that this active snubber simply wont be fast enough
to turn the device back on in time.  Be sure your model includes all
the main buss inductances as well as the delays inside of the

There is always the RCD snubber...

Steve Ward

On 1/21/07, Tesla list <mailto:tesla@xxxxxxxxxx><tesla@xxxxxxxxxx> wrote:
Original poster: "K. C. Herrick" <mailto:kchdlh@xxxxxxx><kchdlh@xxxxxxx>

I'll ask Chip to post
a simulation-schematic illustrating what I have in mind.

I'd like to ask if anyone has had experience with using a
power-MOSFET in its avalanche mode in an active snubber circuit.  In
my posted circuit, Q4 is a power-IGBT prospectively driving an
untuned Tesla-coil primary, with secondary-return feedback to sustain
oscillation.  In hardware, I would implement a push-pull
configuration, with a center-tapped primary and a pair of IGBTs.

The snubber circuit involves Q1, Q3 and the associated
components.  Absent snubbing, negative-going Q4 drive passes through
D9 and turned-on Q3 while positive-going drive passes through R1,
C4/R4 and D5.  (In simulation, C4/R4 was necessary to preclude
oscillation during the snubbing.)  Thus negative-going drive is
relatively fast while positive-going drive is relatively slow--as
necessarily implemented in push-pull or H-bridge configurations.  But
when Q4 cuts off every half-cycle, TX1's resultant overshoot reaches
~800 V and Q1 avalanches.  Q1's current then passes thru D8, C4/R4
and D5, shutting off Q3 and thus the negative-drive, and rapidly (and
briefly) turning on Q4 to snub the overshoot.

The circuit of D6, C3, D1 and R9 acts to divert Q4's current during
each turn-off so as to diminish the power dissipation in Q4, and also
to slow the rise of TX1's overshoot to give time for the Q1 circuit
to operate.  In effect, turn-off power dissipation is transferred
into R9 each time Q4 turns on, easing the stress on Q4.  (In hardware
for D6, I'd plan to utilize the otherwise-unused reverse-diode of a
half-H-bridge "brick" of which Q4 is a part.  The diode needs to be
fast and it needs to have a large reverse-voltage-withstanding.)

Simulation shows that Q1, in avalanche, needs to conduct ~2 A--which
goes thru R1--while the voltage across it is 800 V.  That's 1600 W,
but only for ~1 us out of 8 (for a ~120 KHz Fr).  That cuts the mean
dissipation to 200 W during the pulse burst, and with a 1% sparking
duty-cycle, that's cut further to only 2 W.  So the question is...can
a IRFBE30 MOSFET or the like withstand the 800 V and at the same time
the 2 A--even at only a 12% x 1% = 0.12% duty cycle?

I'd thought of using an MOV in the same circuit, or perhaps a string
of them, instead of an avalanched MOSFET, but I'd be worried about
the capacitance of the MOV(s).  Any ideas about that, as well?

Ken Herrick