RE: Recent s.s.t.c. work

["Tesla list" <tesla@xxxxxxxxxx>]

Original poster: "BNJ" <firebee@xxxxxxxxxxxxxxx>

Ken,
Ok on the transformer drive negative going input. That should work as you
have described and your transformer driver sounds a reasonable
configuration.

I'll volunteer another few speculative comments to consider.

First, it's possible that the driver doesn't like directly driving the
equivalent input capacitance at the IGBT gate and increasing R6 as you have
done, is effectively increasing the the driver output impedance to stabilise
its response. This is similar to the effect that happens with OpAmps when
they drive directly into too large a capacitive load.

Second, you haven't described whether you are actively driving more than one
IGBT (ie whether you are testing in half or full bridge configuration ?)
when you have the bridge supply active. Assuming you are driving at least a
half bridge, you should investigate whether you have any overlap (at the
driver outputs) between anti-phase pairs. If you study IGBT data sheets and
application notes you will observe that they generally turn off slower than
they turn on. That means that even with perfect antiphase drive signals, a
half bridge can have very substantial cross-conduction (shoot through)
current spikes (I've measured them!). If your drive signals are overlapping
at all due to unequal hi-low/low-hi propagation delays in the drivers, the
situation is even worse and the transients at the half bridge centre inject
unexpected energy back into the drivers. I have experienced driver output
device heating and failures at low bridge supply volts specifically from
this effect.

FYI - I have long run my brick bridges with adjustable dead-time
non-overlapping antiphase clocks. This eliminates any IGBT shoot through
completely and the drivers only need to contend with the Miller capacitance
charging/discharging effects. The down side of dead-time is that this adds
to the delay around the coil feedback loop and exacerbates non-zero crossing
switching of the IGBTs. I've cured all the loop delay issues as well by
including an adjustable phase advance system (not PLL) in the controller.
Zero crossing switching errors are then negligible.

Third: Another point to consider is the opto-coupler. The driver circuitry
is being taken for rapid 'rides' between the bridge supply rails. One
importance parameter for the opto's is the Common Mode Rejection slew rate.
When you get to 400V supply rails and IGBTs switching at around 200nsec, the
driver side of the opto is swinging at 8000V/usec with respect to the LED
input side of the opto. Capacitive coupling across the opto device can
result in erratic behaviour. The CYN17-3 data sheet I found didn't seem to
spec the CMR slew rate. I recommend you consider an opto with 10,000 to
15,000 V/usec CMR performance once you get any substantial supply volts on
the bridge. Optos with this CMR performance are available and usually have
internal electrostatic screens to shield the LED from the opto output
section. Another point with the CYN17-3 is that it is dead slow in terms of
propagation delay.

Fourth: The capacitance between windings of the input transformer needs to
be small, otherwise energy from the IGBTs is feeding back via the driver
output section components to charge/discharge the input transformer
interwinding capacitance.


Regards
Bevan J






-----Original Message-----
From: Tesla list [mailto:tesla@xxxxxxxxxx]
Sent: Wednesday, 29 March 2006 11:16 AM
To: tesla@xxxxxxxxxx
Subject: Re: Recent s.s.t.c. work


Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

BNJ (& all)-

Thanks kindly for your comments.  The drive from the transformer to
the TCH-DRVR circuit is about 27V peak.  Perhaps you overlooked D7,
which couples negative-going drive to the Q2/Q3 bases.  And since the
drive (whatever its level) not only drives Q2 & Q3 but at the same
time charges the +/- supply capacitors thru D1 & D2, ipso facto it
swings over the full range (less the D1/D2 drops) of the + and - supplies.

I'll be better able to gauge the drive capability of the transformer
(& its driver) when I'll be able to crank up the h.v.  Then I'll be
driving the IGBTs' Miller capacitances.  From what I can tell so far,
it will be sufficient--tho Murphy's Law says "no way", of course.  I
drive the 3" o.d. ferrite toroid transformer differentially with two
D44H8/D45H8 pairs so I think that's a pretty husky source for the 4
IGBT circuits.  And those two transistor pairs--and the
transformer--do not, of course, need to provide the peak currents to
the IGBT gates; those currents come from the C1/C2 capacitors in the
4 TCH-DRVR circuits.

You're right to question the Vcc capabilities of Q2 & Q3; perhaps
they're a bit close at ~54V applied.  But the CNY17-3 is rated at 70V
breakdown, c-e.  The bipolars should run at least for a while, until
when & if I fix the major problems!

You mentioned in passing my use of the opto-coupler.  Its
LED:transistor breakdown is, of course, way in excess of what I
see.  And it is used, as I had noted, not to pass signal per se but
only to gate on, for the duration of the spark event, the signal that
passes thru D6 & Q1.  That feature seems to work nicely.

As I've just posted, my current baffling problem remains overheating
of Q2, D8 and R6.

KCH



Tesla list wrote:
>Original poster: "BNJ"
><mailto:firebee@xxxxxxxxxxxxxxx><firebee@xxxxxxxxxxxxxxx>
>
> >From a quick perusal of your schematic, I suggest you may have some
>fundamental architectural and device issues if the actual hardware conforms
>with the circuit diagram. While the points below don't directly answer your
>questions, they are issues that need to be sorted before you go any further
>and are probably significant contributors to your observed hardware
>behaviour.
>
>First: Q2/Q3 are an emitter follower pair and need their bases to be driven
>with an input that swings substantially across the full range of required
>IGBT gate swing (neglecting Q2/Q3 base emitter drops). While Q1 will
>actively pull the drive to Q2/Q3 high, there is nothing to actively pull it
>low shown in your schematic other than R4/R5 and this will be relatively
>slow given their values. Hence Q2/Q3 would spend undesirable time in a
>quasi-linear state in a high to low transition. Not good !
>
>Second: give some more thought to the drive level required for Q2/Q3. They
>will be driving short duration high current pulses into/out of the IGBT
>gate, possibly 10's of amps peak, given your driver supply levels and the
>value of R6 and the IGBT internal gate resistance. The current gain of the
>D44H8 and D45H8 can be as low as 40 with a collector current of only 4A
(and
>will be even less with higher collector current). The drive to Q2/Q3 needs
>to be something that is fast, can swing nearly the full +/-supply range and
>can drive short term peak currents of amps into/out of Q2/Q3 bases
>respectively. This is one of the challenges in trying to use a bipolar
>emitter follower complementary pair and why many of us go for MOSFETs
>instead.
>
>Third: The Vce Absolute max of Q2 and Q3 is 60V (from data sheets I looked
>up). You are at that rating if you are driving with +/-30V supplies. That's
>asking for trouble. The Vce max of Q1 is 30V and Vcb is 50V (from a data
>sheet) and this also represents marginal design at best! I didn't look up
>the specs on the CYN17-3 but it is worth checking as well. Depending on the
>transistor models in your simulator, these device characteristics might not
>be well modelled and giving you a less than a true view of actual circuit
>behaviour.
>
>I commend your efforts so far, including your attempt at using opto
couplers
>as an isolation method. I have two variants of brick drivers designs, one
>using complementary MOSFETs and gate drive transformers and another using
>high speed optocouplers and complementary MOSFETs, although the latter is
>substantially more complex than your present design approach.
>
>Regards
>
>BNJ
>
>-----Original Message-----
>From: Tesla list [<mailto:tesla@xxxxxxxxxx>mailto:tesla@xxxxxxxxxx]
>Sent: Tuesday, 28 March 2006 7:53 AM
>To: <mailto:tesla@xxxxxxxxxx>tesla@xxxxxxxxxx
>Subject: Re: Recent s.s.t.c. work
>
>
>Original poster: "K. C. Herrick" <mailto:kchdlh@xxxxxxx><kchdlh@xxxxxxx>
>
>To anyone giving any thought to this:  I'm just seeing, with further
>perusal of the simulation, that a) I still have a phase-shift problem
>thru the loop (causing non-z.c. switching); but more to the immediate
>point, b) while the drive to the IGBT gate looks clean, there is a
>significant (simulation) oscillation occurring in the currents of Q2
>and D8!  A burst of several hundred mA peak, occupying most of
>every-other half-cycle (of the simulated spark-burst of
>cycles).  Frequency, ~17 MHz.  So...that may be what's happening in
>the hardware.  I'll be trying to find out why that is, in the simulation
>first.
>
>KCH
>
>Tesla list wrote:
> >Original poster: "K. C. Herrick" <mailto:kchdlh@xxxxxxx><kchdlh@xxxxxxx>
> >
> >Here's a bit of a puzzle; perhaps someone can offer a clue toward
> >solving it.  I post
> >
>
><http://www.hot-streamer.com/temp/tch-drvr.jpg>http://www.hot-streamer.com/
>temp/tch-drvr.jpg
> >
> >
> >, the schematic of my IGBT driver.  I briefly repeat how it is to
> >work: Input excitation is present all the time, keeping  C1 & C2
> >charged via R1, D1 & D2.  Negative-polarity input signal, via D7, Q3
> >& R6, keeps the IGBT's gate at ~-27V (with R5 holding it there
> >between half-cycles).  Q1 is kept off between spark events by A1 being
on.
> >
> >During each burst of excitation to turn on the IGBT, A1 is turned
> >off.  R3 turns Q1 on during positive half-cycles of the input.  D6 &
> >Q1 pass the positive-going signal to Q2/Q3 and their output drives
> >the IGBT, between ~+ and - 27V (perhaps ~26, with the Q2 & Q3 b-e drops).
> >
> >I've incorporated D8 & D9 to soak up any voltage overshoot that
> >might occur at the gates; one or the other is to conduct at an
> >overshoot and clamp it to the voltage of C1 or C2.  I would have
> >expected neither D8 nor D9 normally to conduct.
> >
> >Testing so far with no H.V. applied to the IGBTs, I see good
> >IGBT-gate waveshapes: rise/fall of n.g.t. 200 ns, -27 to
> >+27V.  Smooth as can be with just the barest ringing top & bottom
> >using a 100 MHz scope & probe.  But here's the rub:  With less than
> >10% duty cycle, on vs. off, Q2 >>and D8!<< rather quickly become
> >hot.  Why Q3 does not become at least equally as warm as Q2, and why
> >D8 warms up >>at all<<, I cannot fathom.  Anyone have a thought on it?
> >
> >Ken Herrick
> >
> >Tesla list wrote:
> >>Original poster: "K. C. Herrick" <mailto:kchdlh@xxxxxxx><kchdlh@xxxxxxx>
> >>
> >>Hello Steve-
> >>
> >>No, I decided to do away with that, on the basis of an additional
> >>simulation.  The simulation showed that I could get a proper phase
> >>shift--yielding the correct phase for feedback--by taking feedback
> >>from a 1-turn loop around the primary rather than from a current
> >>transformer.  So that's what I've implemented.  I still have the
> >>phase-shift assy and if this is a total failure I will resurrect
> >>that--provided that my energy for this Tesla stuff continues to
> >>hold out to a sufficient degree.
> >>
> >>In the next day or so I'll bit the bullet & crank up the juice bit
> >>by bit.  And I do have the camera handy!  In fact, as I've
> >>mentioned before, I can now take scope photos with it.  I just hope
> >>there'll be some good photos to take.
> >>
> >>Ken
> >>
> >>Tesla list wrote:
> >>>Original poster: "Steve Ward"
> >>><mailto:steve.ward@xxxxxxxxx><steve.ward@xxxxxxxxx>
> >>>
> >>>Hi Ken,
> >>>
> >>>Will you be employing your delay register on this next attempt to try
> >>>and compensate for delays?  I hope that works as expected.  Be sure to
> >>>have a camera handy to take pictures of the sparks!
> >>>
> >>>Good luck, let us know how it turns out.
> >>>
> >>>Steve
> >>>
> >>>On 3/24/06, Tesla list <mailto:tesla@xxxxxxxxxx><tesla@xxxxxxxxxx>
wrote:
> >>> > Original poster: "K. C. Herrick"
><mailto:kchdlh@xxxxxxx><kchdlh@xxxxxxx>
> >>> >
> >>> > I see that my last posting on this topic was in December.  In the
> >>> > interim I've been slothful to a fault (altho happily busy for 3 of
> >>> > the weeks entertaining our Most Perfect Granddaughter, 2 1/2,
> >>> > visiting from Berlin).  But I have now gotten to the stage where I'm
> >>> > ready to put the H.V. to it once again.  I've checked the gate
> >>> > waveforms & all 4 appear OK.  Next, it's... turn up the variac &
> >>> > watch for the smoke.  It's only trepidation, accumulated from years
&
> >>> > years of such practice, that keeps me from doing it today; So
perhaps
> >>> > I'll first just sit & think about it for a while...
> >>> >
> >>> > Someone asked, after I reported my last failure (death of an IGBT
> >>> > brick), what might have caused it, and at the time I didn't
> >>> > know.  But while rebuilding the drivers, I discovered that I had
> >>> > positioned a wire-wrap pin, in one of the gate circuits, so that,
> >>> > when I fastened the board down above the mains capacitors, the pin
> >>> > pressed against one of the capacitor terminals--hidden from view, of
> >>> > course.  I didn't locate the source of the resultant smoke until I
> >>> > started rebuilding.
> >>> >
> >>> > As I've already reported, I utilize NPN/PNP emitter-follower
> >>> > driver-pairs for each of the 4 H-bridge IGBTs, transformer-driven,
> >>> > with the 4 transformer signals always applied (from my "pilot
> >>> > oscillator")--and now rebuilt with opto-isolators acting to gate-on
> >>> > drive to the NPNs during the spark-event times.  That way, all 4
gate
> >>> > voltages are kept at -28 or so between sparks by the continuous
drive
> >>> > from the PNPs.  As before, the continuous transformer signal also
> >>> > serves to keep the + and - drive-supply electrolytics charged up.
> >>> >
> >>> > So stay tuned, so to speak--& don't be startled by smoke seen coming
> >>> > from the vicinity of California; it'll only be me once again.
> >>> >
> >>> > Ken Herrick
> >>> >
> >>> >
> >>> >
> >>> >
> >>> >
> >>>
> >>
> >>
> >
> >
> >
>
>
>