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3rd harmonic trap
- To: tesla@xxxxxxxxxx
- Subject: 3rd harmonic trap
- From: "Tesla list" <tesla@xxxxxxxxxx>
- Date: Mon, 21 Mar 2005 11:35:56 -0700
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- Resent-date: Mon, 21 Mar 2005 11:36:17 -0700 (MST)
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Original poster: "Jolyon Cox" <jolyon@xxxxxxxxxxxxxxxxxxxxxxxx>
Dear List
I am wondering whether it would be possible to use a parallel-resonant LC
circuit in series with the primary of an SSTC as a "trap" to suppress the
unwanted 3rd harmonic mode of oscillation.
Does anyone know if this is feasible or even desireable?
Jolyon