RE: SSTC modelling- ISSTC current limiter

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "Steve Conner" <steve.conner-at-optosci-dot-com> 

 >What if we used a microcontrol with something like the following
 >algorithm:

It's definitely the right kind of way to go. But I think it could be even
simpler than what you describe. After all the ISSTC is self resonant so you
don't need to bother with tuning. The DRSSTC is not, but the tuning seems
broad enough to set and forget.

So what I'm thinking is a current limiter hooked up to the interrupter. It
measures the peak primary current, and terminates the burst if it gets above
a safe...ish :) value. If the burst is terminated by the current limit,
rather than the interrupter timer, it should also light some kind of warning
light to make you aware of the fact.

There would have to be some gating to make sure that the burst was only
terminated at a natural switching instant, IOW, the enable signal to the
gate drivers should go through a D-type flip-flop that is clocked by the
gate drive signal. Otherwise it can try to turn off at a peak of primary
current, which is not good.

The current limit would be easily done with a Rogowski coil and a window
detector made from a couple of comparator chips. I try to avoid using a
microcontroller in any "mission critical" part of a SSTC where it could blow
out your pricey IGBTs if it glitched or crashed.

Steve C.