Re: A belated s.s. realization

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "jimmy hynes by way of Terry Fritz <teslalist-at-qwest-dot-net>" <chunkyboy86-at-yahoo-dot-com>


Hi Ken,

This happens in h-bridge and half bridge circuits too, and is easier to 
visualize than in a  "daisy chain". Although it is more evident in high 
pulsed power SSTCs, CW SSTCs do this a little bit also. pspice really makes 
it easy to understand.

With no load, the current wave form is triangular, and is 90 degrees out of 
phase with the voltage. During the first few cycles, the current is almost 
all positive, so the bottom MOSFET in the half bridge doesnt see much 
current. The current starts flowing through the fet near the end of the 
cycle.  With no magnetizing current, the current is a sinusoid, and is in 
phase with the voltage. At the time of switching, there is no current 
flowing, so the diodes dont do anything. In the real case, the catch diodes 
carry current for the first part of the cycle, then is carried by the 
MOSFETs. The circuit still functions normally; there is still a square wave 
voltage on the primary. the increased off center current just heats up the 
fets, diodes, and makes the whole thing more confusing. There is no reason 
to make any changes if it works :-)

I hope this helps, but it is hard to explain something through only words. 
playing around with pspice really helps.

  Tesla list <tesla-at-pupman-dot-com> wrote:
Original poster: "K. C. Herrick by way of Terry Fritz "

Those of you who have paid attention to my "current-ring" s.s. primary
design may want to read this. As you will recall, I employ two loops of
primary conductor connected together with energy-storage capacitors.
Each loop incorporates multiple switch-transistors and each set of
transistors acts alternately with the other set to pass current from the
capacitors unidirectionally through first one loop, then the other, thus
setting up the alternating magnetic field that excites the secondary.

Each transistor is protected against reverse--and excess forward--voltage
by the "catch" diode that is connected across its opposite transistor, by
coupling via the associated energy-storage capacitors. But there lies
the rub. It appears that the circuit is a bit like t! he proverbial bee:
unable to fly according to known aerodynamic principles, it flies anyway
since it does not know that.

When one of the sets of transistors is conducting, all is fine: current
flows in a "daisy chain" through the transistors, the primary conductors
and the storage capacitors, setting up that direction of primary-current.
But then, when that set of transistors shuts off at the end of its
half-cycle and the other set becomes turned on, each transistor of the
other set finds that it is paralleled by a catch-diode that is mightily
conducting in its forward direction, catching the inductive overshoot of
the opposite set of primary conductors. That forward direction of diode
conduction places a low voltage of the wrong polarity across each
transistor that at that moment is supposed to begin conducting.
So--those transistors do not begin conducting and the circuit doesn't
"fly".

Except...it does fly; or at least,! is has been doing so. So those of you
who may have been considering use of a similar configuration, take heed.
While I take 5, likely a lot more than 5, trying to figure out a) why it
has worked at all and b) how to change it so that it works
understandably.

Ken Herrick



Jimmy