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Re: Paralleling FET's
Tesla List <tesla-at-pupman-dot-com> on 18.10.99 12:22:01
To: tesla-at-pupman-dot-com
cc: (bcc: Marco Denicolai/MARTIS)
Subject: Re: Paralleling FET's
>Original Poster: "Jim Lux" <jimlux-at-jpl.nasa.gov>
>
>I WOULD but ferrite beads on the gate leads though, and check for spurious
>oscillation. Paralleled FET circuits seem to be more prone to oscillation,
>because the high "switched output" couples back into the gate.
I have myself learned "the hard way" about that, by burning ten+ IGBTs (1200V
35A devices). The problem is also recognized by Motorola and is called
shoot-through current: a rapid change in Vgs will induce a voltage spike to the
gate (for many aspects you can treat IGBTs and FETs as equivalent devices).
For instance, in a H bridge configuration, the low-side FET turning on will
induce a spike on the gate of the high-side FET, turning it more or less on. If
it gets on, you could also blow the pair (as I did many many times) as you are
making a shortcircuit to your power supply through the FET pair.
The solution to this problem is to use a low impedance for gate drive or,
better, a low impedance for turning OFF and a slightly higher for turning ON. A
suitably slow turning on and a solid current sink when keeping in off state
will
reduce EM emission, noise and cure the gate spike.
For instance use a 90 ohm resistor in antiparallel with a 10 ohm resistor in
series with a fast (low Trr) diode for gate drive.
Another reason for malfunctioning is FET lead impedance, but this is
trivial and
anyone should know about this already.
Regards
PS. Ever seen a HV diode tossing out its silicon die in flame from its case?