Re: Capacitance of a coil

To: tesla-at-pupman-dot-com
Subject: Re: Capacitance of a coil
From: Scott Stephens <Scott2-at-mediaone-dot-net> (by way of Terry Fritz <twf-at-verinet-dot-com>)
Date: Mon, 18 Jan 1999 12:20:59 -0700
Approved: twf-at-verinet-dot-com

At 04:13 AM 1/18/99 -0700, you wrote:

>Original Poster: "Antonio Carlos M. de Queiroz" <acmq-at-compuland-dot-com.br> 
>
>I wrote:
>
> (I didn't try yet, as
>it takes too long to complete. Will someone translate it to some
>-fast- language, as djgpp C?)
>

I strongly urge assembly. Not that I've done it (for the pent yet), but
Intel and AMD web sites both have app notes on how to optomize code and a
few DSP examples (like matrix op's) for the Pentium,

(http://developer.intel-dot-com/design/perftool/cbts/mmxintro/mmxdown.htm is one
of a few sites)

 so your crunchy routines execute in L1 and L2 cache's, your pipelines flow
and don't flush, and if you have it, your MMX can munch matrix doing
parallel integer multiplys.

That Laplace routine (relaxation algorythm?) might be optimized too. There
is a very popular DSP and numerical method book on the web:

http://sigma.ire.pw.edu.pl/numrcp/

When it works right, you can do 100's of MIP's on your 100MHz+ pentiums.
Poor code may execute, but can result in multi-cycle penalties every time
the pipeline flushes a poorly guessed execution path.

And while I'm critiquing Terry's good work I can't do perfect, I would make
the output for the free VRML viewers, rather than that awfull Microsh*t
Excell spreadsheet :)