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Re: Solid-state TC - transformer design
Greetings
Harri wrote:
>Minimize leakage inductance
>by interleaving primary and secundary. Minimize secundary capasitanse.
>If you do not take those precautions they may lead into lots of trouble.
>They did for me with traditional pwm-drives. With high turns ratio
>you may have secundary capasitance refled to primary side at tens
>of nanofarads easily!
Problem if you interweave primary and secondary then you increase
the capacitance problem. The arrangement that I use: primary on
the bottom then secondary (ground end), 3 layers, at least minimises
the voltage difference between the layers and hopefully the lowest layer
of the secondary will screen the effects of the upper layers. Could a layer
of aluminium foil be wrapped around the primary - insulating the overlaping
ends to avoid a shorted turn. This would halve the capacitance, but add an
extra layer.
The only way I can see out of this is to use a lower ratio output transformer
and then connect via a LC resonator as someone suggested earlier. Probably
yeilds a different set of problems! I remember that someone on the list was
discussing doing this - anyone tried it - does it work? How do you tune the
LC resonator?
Have fun,
Alan Sharp.