Steve,
The benefit of capacitive VARs that “correct” the phase displacement caused by the inductive reactance is realized as current and voltage being more aligned and reduction in the current drawn from the mains in relationship to the true power. The reduction in current draw is ONLY realized ‘upstream’ of the PFC placement in the circuit and the higher amperage associated with phase displacement will still be present in all of the components ‘downstream’ from the PFC bank. Therefore, imho, the choice between the options you mention would be a matter of personal preference (and the current load that your downstream components could withstand) and either would result in a decrease in amperage drawn from the mains.
David
Sent from my iPhone
> On Jan 3, 2019, at 10:42 PM, Steve White <steve.white1@xxxxxxxxx> wrote:
>
> What is the correct topology for the PFC capacitor placement when a ballast is being used? There are 2 options as follows:
>
> Option 1: Variac followed by PFC capacitor followed by the ballast followed by the pole transformer
> Option 2: Variac followed by ballast followed by PFC capacitor followed by the pole transformer
>
> I have been using option 1 which appears to work correctly. I suspect that either option is valid. The only difference between the 2 would be a different value of capacitance required for the same amount of power factor correction.
>
> Steve White
> Cedar Rapids, Iowa
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