Re: [TCML] pwm with gate drive transformer

[Scott Bogard <sdbogard@xxxxxxxxx>]

Hi Mike,
     I assume when you say the secondary waveform you mean of the gate drive
transformer and not whatever it is driving.  With that said, can I not just
tie the secondaries to the ground pin of the FETs they'll be driving to make
sure they do not shift, or does it not work that way?  Also if the gate
drive transformer is driving a half bridge, will it work with PWM, in my
mind it should, as it will never be shorted due to the capacitors on the
false half of the bridge, but again I know little of how all this stuff
actually works...  Lastly if it does shift, I can probably protect the fets
with a zener diode, but will they not turn on and off properly if I do?
Thanks.

Scott Bogard.

On Fri, Oct 14, 2011 at 10:41 AM, Michael Twieg <mdt24@xxxxxxxx> wrote:

> If you want to use a GDT at duty cycles other than %50 you have to take
> some
> precautions.  First you'll need a DC blocking capacitor on the primary to
> prevent DC current from saturating it.  Second, the secondary voltage
> waveform will inherently have have no DC offset, and therefore the waveform
> will "shift" up and down depending on duty cycle.  For example, for a 1:1
> GDT driven with 20V peak to peak on the primary, at 50% duty cycle the
> secondary will give the same thing out (Vmax=10V, Vmin=-10V).  However, if
> you drive that at D=25%, you'll get Vmax=15V and Vmin=-5.  As D approaches
> 0%, Vmax will approach 20V and Vmin will approach 0V.  Conversely, the
> opposite happens at D>50%.  As D approaches 0%, Vmax approaches 0V and Vmin
> approaches -20V.
>
> So there are limitations to the duty cycle range you can use.  The lower
> range will depend on the maximum gate voltage the transistor can withstand.
> The max limit will be determined by the minimum Vgs needed to keep the
> transistor operating in its linear region (for FETs) or saturated region
> (bipolar devices).
>
> -Mike
>
> On Thu, Oct 13, 2011 at 8:44 PM, Scott Bogard <sdbogard@xxxxxxxxx> wrote:
>
> > Hi all,
> >     Doing some research on gate drive transformers attempting to
> understand
> > how they work, and it occurs to me most of the schematic I am looking at
> are
> > fixed at 50% duty cycle.  Is it harmful to use one with a variable duty
> > cycle, does this not develop a good voltage and cause fets to run out of
> > saturation, or should it work fine, are there practical limitations?  If
> > anyone can point me to some good literature I would appreciate it.
> >
> > Scott Bogard.
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