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Re: [TCML] SSTC opinions solicited

did you phase the xsistors prior to running power in the circuit?  If you
get them out of phase it's like switching a load into a short and the igbts
or mosfets rapidly fail.  With mosfets it's also a good idea to insert a
current limiting device 10-15 amps into the circuit to limit the current
while carefully measuring it thus preventing shorts, etc, from damaging
something.  This is later removed when proper circuit operation is verified
and measured.

also, verify your coeff of coupling in JAVATC.  Keep it below 0.2.  I never
run higher than 0.18 on my DRSSTC designs.  Some experimenters do, but
usually with eventual failure.

Dr. Resonance

On Sun, Nov 1, 2009 at 3:14 PM, Ken or Doris Herrick <kchdlh@xxxxxxxxx>wrote:

> Now it begins again for me: the "make it work" phase of a new design.
>  /Always/ a bummer.  This time, it was initiated just today with the
> almost-immediate failure of a $54 transistor.
> As some may recall, I'm attempting to resuscitate my previous SSTC.  In the
> reincarnation I'm using 6, STE40NK90ZD 40A/900V MOSFETs in a ring
> configuration.  But--just in case, I have bought only 2 of those, and am
> gradually bringing up the supply voltage with 4, IRFP460As temporarily in
> the circuit instead of the $54 STEs.
> So...I gradually bring up the supply voltage to around 200 across each
> transistor, without the secondary in place, and pulse the primary when
> suddenly--what would you think happens?  A big, loud  /Crack!/, that's what,
> with the supply voltages pulled right down to 0--of course.  And which
> transistor would you think failed, exhibiting 500 ohms or so gate:source?
>  Well--of course: one of the STEs.
> In this design, 3 transistors in series drive the primary + and the other
> 3, -, with the same (isolated) supply voltage applied to each transistor
> (ultimately to be ~300 V).  And they're all driven from identical floating
> drivers, all of which check out fine, both prior to and after the failure,
> each providing 0 to +28V drive pulses.  The failed STE exhibits not a hint
> of exterior damage: all pristine, and its source:drain is not shorted, per
> the ohmmeter.  So where did that loud Crack! come from, do you suppose?
> I do find a likely reason for some kind of failure:  I messed up on the
> crossover-delay, allowing each set of 3 to turn /on/ ~1 us before the others
> turn off rather than the other way around.  Not good since all 6 are
> daisy-chained in a circle with their respective power sources, but easily
> rectified in this case merely by swapping 4 plug-in inverting/non-inverting
> driver-ICs.  But why did gate:source fail and not (apparently) source:drain?
>  And why the $54 one rather than a lower-rated $5 one?
> Each transistor is protected by a) a diode limiting Vs-d to twice the
> supply voltage and b) a M.O. varistor directly across, source:drain.
> One other possible but not likely contributor:  Each floating d.c. power
> source consists of 2 uF paralleled by 1000 uF.  At that particular
> transistor and that one only, for convenience I connect the 2 uF to the
> source terminal adjacent to the gate terminal and the 1000 uF to the source
> terminal in-line with the drain terminal.  The ST data sheet makes no
> distinction between the two source terminals, and they are the same physical
> size, so I have to assume (so far) that there is none.  But is there a
> distinction?...
> (And one other, prior, failure will entertain:  In my l.v. circuits I have
> a 74HC14 Schmitt-trigger gate used as a simple oscillator, chugging along
> all the time at 70 KHz or so.  When I turned up the h.v. a bit and pulsed
> the ring-circuit (and at that time, I had the crossover-delay correct), that
> oscillator would quit.  Hang up at ~2.5V in & out.  Its /Schmitt quit/, so
> to speak.  Wouldn't recover until I turned off the +5, then on again.
>  Really weird.  Tossing that IC out and substituting another one cured the
> problem.  1st problem like that, for me, literally since ICs were invented.
>  I suspect it had to do with excess cross-coupling amongst the other 5 in
> the package.  Perhaps when I fired up the primary, producing its nearby EM
> field, that field caused it; maybe some connection was loose inside the IC,
> producing a floating gate. )
> So, can anyone help shed light on this before I spend myself into the
> poorhouse on more STs?
> Ken Herrick
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