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Re: JK Flip-Flop in Orcad

Original poster: "Gerry  Reynolds" <gerryreynolds@xxxxxxxxxxxxx>

Not necessarily. A JK FF will wake up in an unknown state for sure. You can initialize it with either a PRESET or CLEAR (but not both), or you can clock in a 0-1 or a 1-0 into the JK inputs. This will put the flop into a known state. Clocking in a 1-1 into the JK inputs will toggle the flop from one unknown state to the opposite unknown state (nothing gained).

Gerry R.

Original poster: "Steve Ward" <steve.ward@xxxxxxxxx>

Oh here we go ;-)

Ok, with the PRESET and CLEAR inputs, you always have to cover your
behind and toggle them, then you can leave them where you want them.
I usually use a VPULSE on each one with a delay of 1uS (usually plenty
of set up time) and going from a 0 to 1 or a 0 to 1 to 0 (1
representing 5V or whatever, and note the delay takes care of the
first 0 in the sequence).  Try not to set both inputs at the same
time, either :P.  I remember always having to "prime" my flip flop
simulations with a few uS of getting them all ready.  If you dont do
this, you will either get X (dont care) outputs, or on occasion ive
had the flip flop behave strangely.

Its quite annoying to add all sorts of extra voltage pulses in the
simulation, but i dont know of any other work around (i wonder if
there is some "initial condition" for logic chips in pspice?).

Steve Ward

On 1/12/07, Tesla list <tesla@xxxxxxxxxx> wrote:
Original poster: Finn Hammer <f-h@xxxx>

Microsim/Orcad aficionados:

Attempting to create synchronization between. 2 digital signals, I
have started to test a 74HC109 flipflop against it`s truth table in Orcad 9.2.

The first problem I stumble upon is that when I put a voltage pin on
Q and notQ, the probe program shows traces that are without a voltage
scale. I was expecting it to show 0V and 5V. Why is that so?
At times, it shows 2 red lines instead of a Low or a High, what does that mean?

But worst of all, I cannot make it follow the truth table:
If I tie PRE and CLR to positive, then tying J high and K low should
make the outputs toggle by each clock transition.

They don`t. I get the dual red lines.

So I am stuck here, seeing little sense in progressing further before
the model conforms with the truth table.

Any help is appreciated.

If I configure it as a T type FF by tying J and K together it does
perform as it should, but that is not good enough.

The model I use is available for download here:


Data sheet is here:


Cheers, Finn Hammer