RE: PLL SSTC

["Tesla list" <tesla@xxxxxxxxxx>]

Original poster: "Leigh Copp" <Leigh.Copp@xxxxxxxxxxx>

Hi Rajesh,

The CD4046 is a marvellous hybrid device that I debuted in the 70's (I
believe) and revolutionized the control of load resonant solid state
induction heating power supplies, among other things.

You could certainly use the "in Lock" signal, however the problem that
typically arises is something like this:

The phase comparator picks up on noise, and then adjusts the VCO
(Voltage Controlled Oscillator) output higher to compensate.

The phase comparator of course then "sees" an even greater error, and
eventually rails the VCO output to whatever Fmax that has been
determined by the external oscillator timing components.

Now whether the IGBT's go into hard switching or not is largely
determined by the power circuit. In full bridge resonant inverters, what
can happen is that the tank circuit begins to look purely capacitive (as
the impedance of the inductor becomes much greater than that of the
capacitor), and the tank behaves as an integrator.

This has the effect that the square wave voltage is integrated to a
triangle wave which the PLL will have no trouble at all locking on to,
due to the relatively low dV/dt.

The bigger problem here that I have seen is that it is very easy to
exceed the maximum switching frequency of the IGBT when the PLL "runs
away" as described above. Either the switching losses become excessive,
or the tail current time approaches the dead time, and you end up with a
commutation fault (shoot through - top and bottom of the same side of
the H-bridge on simultaneously). There is also a limit to the amount of
current the gate will handle. It takes a certain amount of charge to
turn on the device, and the higher the gate drive frequency, the more
RMS current flow, and the more gate heating will take place. This is not
a well documented failure mode, but one I have observed in larger
(1000A, 1400V) devices at upwards of 10 kHz.

So now here is how you fix it:

1) Careful selection of the low pass filter time constant between the
phase comparator, and the VCO.

And:

2) A low pass, or band pass filter on your feedback to the phase
comparator.

There is an important caveat to be aware of here: Anything you use to
filter, will by definition have a phase shift associated with it. Even a
digitally implemented filter has a group delay. This will skew your zero
cross synchronization. You can compensate for this with delays in your
gate logic but you are now always one cycle of the tank behind. Other
than in a fault however your system can't change frequency
instantaneously so it -will- work.

Most resonant inverter systems get around this by careful selection of
Wn for the PLL (see the CD40446 app notes) which is determined by the
corner frequency of the filter, and the VCO external time constant
components.

The trade off is that your system has a narrower lock in range, so you
have to have the tuning "in the ballpark" before it will work.

So that's my $1.02 worth (or about $0.01 USD) on a Monday cleverly
disguised as a Tuesday.

Leigh

-----Original Message-----
From: Tesla list [mailto:tesla@xxxxxxxxxx]
Sent: September 5, 2006 9:12 AM
To: tesla@xxxxxxxxxx
Subject: PLL SSTC

Original poster: "Rajesh Seenivasan" <rajeshkvs@xxxxxxxxxxx>

Dear forum members,

I believe few members of this forum have used a PLL (4046) to
'auto-tune' the SSTC. I'm trying to build a similar system. I believe
due to noise and (or other reasons?), the PLL would go out-of-tune
and this may (or may not?) result in HARD switching of IGBTs/MOSFETs
in the switching circuits or sometimes may result in huge currents
drawn from the switching circuit. So, is there a way to find out if
the PLL is 'in tune' or not? Has anyone used the 'Phase Comparator
Pulse Output' (Pin #1) in CD4046BC? Please help.

Thanks and regards,
Rajesh.