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A prospective s.s.t.c. input-synchronizer



Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

In my s.s.t.c. project, I need a) a system-signal running all the time to keep the IGBT-drivers' power supplies charged-up and b) a means for seamlessly substituting, for that signal, the feedback signal from a current-transformer when the primary becomes excited. The screen-captured schematic & waveforms at

<http://hot-streamer/temp/tch-synctest.jpg>http://hot-streamer/temp/tch-synctest.jpg

show what I've come up with -- in simulation, that is. It might be useful for others, for deriving a logic-level signal, even if not needing a) above.

I'd initially designed it without D3, D4 & D5. But then I realized that the current transformer would be required to provide a dc current component -- not possible -- since the voltage excursions at Q1's gate were not equal. To correct that, a series capacitor would ordinarily be required. But in this application such capacitor might need to pass an appreciable peak current. So then I thought to add D3, D4 & D5, eliminating the capacitor.

For plus-going I1 current, D4 turns on Q1 & D3, with D1 clamping the collector voltage to ~7V. For negative-going I1 current, D5 turns on Q1 via its emitter and D2. In that case, Q1's collector can only go to ~-1.4V because of D1. In both cases, R2 protects U1 from the slight over-voltage. Notice from the simulation that the mean I1 current is a minimal 2.4 mA out of 10A.

When I1 is providing current, C1's influence is negligible since either Q1's collector current or I1's current via Q1 will rapidly change its state of charge at signal excursions. Absent an I1 input, Q1 remains off and the C1/U1/R3 oscillator functions normally. And Q1's gate:emitter or gate:source voltage is kept within bounds: it cannot go

One could just as well use a MOSFET instead of the IGBT. Better, maybe: I checked it out in simulation & found a mean current of only 1 mA instead of 2.4. So I'll try the MOSFET.

N.B: R1 is required in the simulation; in the real world I'll use a pair of 1Ks at the right sides of D4 & D5 -- to ensure Q1 stays off with no I1 input.

KCH