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Re: SISG PC BOARDS



Original poster: "Gerry  Reynolds" <gerryreynolds@xxxxxxxxxxxxx>

Hi Mark,

These things can be somewhat difficult to calculate. I didnt spend any time figuring out the scale factor on your trace widths and I assume the board is using 2 oz copper (being an outer layer). Im thinking that what you have done is probably reasonable. I believe there are two issues with pc layout - heat generated in the trace (and you need to know the Irms to figure this out), and metal migration (peak current is the issue here and resulting current densities). I just dont have any numbers. Im wondering if you ever turn the board if there is any reason to not fatten up the traces as much as possible.

Gerry R.



Original poster: "Mark Dunn" <mdunn@xxxxxxxxxxxx>


Gerry:

Good question.  Maybe you can help me here.  My trace calculations are
based on pure DC and I do not know how to correct for the high
frequency.  What I did is come close to the cross-sectional area of the
CDE942 leads so on that basis of that I should be able to push 500 amps.

Now here is what I tried with math.  See if you think I'm on the right
track.

Based on simple DC trace calculations I have:

24 amps give a 10 Deg C rise.
38 amps a 38 Deg C rise.

The above values are based on dual(top and bottom) 125 mil traces in 3
oz copper.

Now at 460 BPS I have 2130 uS "off-time" (cap charging time) and 43 uS
"on-time" for ring-up and ring-down with my RSG(Note - Terry's testing
suggests the "on-time" might dramatically increase).  So maybe we can
compute the average current during the whole break cycle to consider the
thermal effect.

If we have 500 amps during the "on-time" and near zero during the
"off-time" then the average current is 43/2173*500 = 10 amps avg
current.

Subsequent to my board design, Terry found the "on-time" might jump to
150uS.  If we use that measure then 150/2173*500 = 35 amps avg current.

Critique of this calc would be much appreciated.

Mark


>Original poster: "Gerry  Reynolds" <gerryreynolds@xxxxxxxxxxxxx>

>Hi Mark,

>How much current do you estimate the traces (high current path) on
>your layout can take??

Gerry R.