Latest v. of s.s. driver

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Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

I'm still plugging away at it.  Here's the latest simulation of my 
s.s. IGBT driver circuit:

http://www.hot-streamer.com/temp/dualdrive-IGBT4.jpg

.  I'd had a problem in the hardware with the Q2/Q5 circuits which 
I'm just correcting per this updated schematic but otherwise it seems 
to work fine.  Altho...no sparks as yet; I proceed cautiously, some 
might say lackadaisically.

V2 drive is applied all the time, in the hardware from a "pilot 
oscillator" when not sparking and from primary-feedback when 
sparking.  The not-sparking drive serves to keep the 270u capacitors 
charged.  Not shown are schottky diodes in the hardware across the 
Q1, Q3, Q7 & Q8 b:c junctions, to bypass charging currents around the 
junctions--altho there should be no problem without them since those 
are TO-220-size transistors.

When not sparking, U1 & U2 are on, keeping Q2 & Q5 off.  Passed to 
the IGBT gates are thus only the negative excursions from Q1, Q3, Q7 
& Q8, via D1 & D3, keeping the gates at -25V or so.  The Q2/Q5 
circuits serve not only to shut the IGBTs off while not sparking but 
also to absolutely control crossover conduction.  When U1 & U2 are 
off, Q2/D7 and Q5/D8 can only pass + going excursions to the IGBT 
gates when the respective Q2/Q5 base potentials become more positive 
than the respective IGBT source voltages.  The connections of R4 & R8 
assure that.  That means that neither gate:source potential can 
commence rising above 0 until the alternate potential starts to 
diminish below 0--assuming, of course, sufficient inter-winding 
coupling within TX1.

Also not shown are 30V zeners across the 4, 270u capacitors, just for 
insurance.  C1, C11, C10 & C7 simulate the IGBTs' input 
capacitances.  And, of course, only 1/2 the H-bridge is simulated; in 
my system, I use a 5-winding toroidal transformer for driving 4 of 
the IGBT-drive circuits together.

D5, D4, D6 & D2 are again for insurance--and in the hardware--to 
clamp any spurious EMI induced onto the gate circuits.  D9 & D10 
protect U1, U2, Q2 & Q5 against any reverse voltages while D7 & D8 
assure that Q2 & Q5 are firmly off while U1 and U2 are on.

Any comments are welcomed!

Ken Herrick