Re: Dan's ultrafast gate drive, schematic?

["Tesla list" <tesla@xxxxxxxxxx>]

Original poster: Jan Wagner <jwagner@xxxxxxxxx>

Hi,

Tesla list wrote:

> Steve Conner wrote:
> ...

Nasty accidents happen with Shift+Del, and www.pupman.com with the 
archives seems to be down... But I did read your post before the accident.

Thank's Steve for the www.scopeboy.com/tesla/classde.pdf thesis!
It was an interesting read, and not just the gatedrive section. :-)

It sure seems tricky with the gate drives to cope with large duty 
cycle changes, and your points about output volt-seconds balance are 
valid. With <3.3V levels, looks like even Dan's circuit can't cope. 
So first I considered coupling the PWM pulse transformer as 
current-signalling to a resistor + LVDS receiver 
(DS90LV018A, >+-200mV signalling).

But in the end I came up with a somewhat different solution: both 
half-bridges have an IR2110 (10ns max mismatch) to do a clean level 
shift job, and TC4422CAT's for 9A peak driving. This should do for 
300..400kHz and the first low-power prototype with IXFX180N10's, 4ohm 
subwoofer, 65V. There might be a HiFi-impairing phase shift between 
the two halfbridges, due to delay mismatches between different 
IR2110's, so probably I'll have to sort through a batch of these 
chips... Too bad HIP408x's only cope up to 80V, otherwise nice chips. 
And I know IR211x's go "popcorn" in SSTCs, but an audio power amp 
hasn't that large E-fields so hopefully they manage to survive... ;-))

About the DSP-SSTC... LOL, it won't be making your PLL/FB SSTC 
obsolete any time soon! ;-)) While the DSP-SSTC hardware is there, so 
it's not entirely vapourware, it still lacks that very crucial 
firmware magic... :)

Thanks for your help!

- Jan