Re: SSSSTC Coil questions for Mr. Steve

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "Steven Ward" <srward16-at-hotmail-dot-com> 

Okay Dave,

Some of your ideas are a bit unclear, but i like the way you seem to 
envision much more which could be done with this design ;)  I will answer 
what i can, and question what i dont understand.


>I understand this now.  A couple more power circuit questions:
>1.  What FET are you using?

For the 4 level inverters, the first 4 fets are IXFN80N50s and the last 4 
are IXFN48N50s.  I know, extremely overrated, but what the heck, i have 
them.  As you probably understand, the lower fets see the most current, and 
the left most see the most (since they have to supply all of the stages 
when the caps charge up).

Spec sheets for these fets (im using the SOT227 versions of course) :

http://www.ixys-dot-com/93001.pdf

http://www.ixys-dot-com/98538.pdf


>2.  What is size, type and voltage rating E storage cascade capacitors
>      are you using?

They are 5uF 400VDC 40L G.E. polypropylene capacitors. High quality ones.
So about .4j each at 400VDC (which i eventually plan on running the coil 
at).  Now, we dont want these caps to discharge much at all on each cycle 
as i understand it... is this the correct way to think?  If the caps 
discharged too much, then the output voltage would sag.  I basically chose 
the 5uf caps because i could get a good deal on them and PSPICE suggested 
as low as 1uf was perfectly fine.  IF the caps are way too small, then the 
output voltage sags to almost nothing (which really threw me on my first 
simulations.. i thought the circuit was bogus.  Then a bit of component 
changes and viola!).

>3.  What blocking diode are you using (P/N, voltage current fast
>      recovery, etc.)?

Hmm, im not sure which blocking diode your referring too.  The only fet 
protection i have are the parallel ultrafast diodes.  Here is the spec 
sheet for them:

http://www.fairchildsemi-dot-com/ds/IS/ISL9R3060G2.pdf

I also use them for the diodes that charge the capacitors for each stage.
They seem like really nice diodes.

>4.  On each GDT winding to FET, what value resistors are you
>      using for gate, gate pull down, and are you using zener (or
>      bi-directional) clamp between gate and source of each FET.

Each gate has a 10 ohm resistor but with a schottkey in parallel with the 
resistor so that the fall times are faster than the rise times.  This is my 
insurance to eliminate the possibility of shoot through as these fets turn 
on a bit faster than they turn off.  There is no pull down, i never saw the 
need for them in my designs so i never even used them.  Also, i have a 14V 
zener to clamp the + part of the gate drive and an 18V zener to snip the 
bottom ( i did this from lack of enough zeners to do them all the same).
The reason is that with the 10 ohm resistor not effecting the fall times, 
there was a large spike that would exceed about 30V.  But, the top of the 
wave form never went much about 12V (so the 14V zener isnt doing anything 
really).


>Thanks for the info...
>-----------------------------------------
>
> >
> >   Maybe a high
> > >power
> > >current loop with indiividual I>V converter transformers at each switch
> > >pair may reduce delays and losses.
> >
> > If i knew more about electronics i would be able to follow you... to tell
> > you the truth, im a freshmen in college and havent take a single course in
> > electronics yet.  I *THINK* i understand what your saying, but im not sure
> > how to design/implement this.
>
>----------------------------------
>Basically wind the primary ONLY on a ferrite toroid. Pass through the
>window of the primary toroid a high current copper loop (1/8 to 1/4"
>copper tubing is perfect).  At each driver PCB have a toroid with number
>of windings for each FET.  Copper tubing would pass through each
>of these FET drive toroids.  The copper tubing makes a one turn loop
>through the window of all the toroids.  The GDT driver now drives the
>entire high current loop, and thereby drives each driver board.

WOW! I LOVE that idea! The only thing i worry about is the leakage 
inductance.  I think it may be worth looking into.  What about just making 
that copper loop THE primary?  Though i suppose that would mean low voltage 
but very high current driving it.  I doooo like the idea though, maybe i 
can test it out ;)


>The advantage of this idea is one HUMONGOUS driver could drive 4X
>as many drivers and they would be synchronized fairly well to each other.
>This would simplify building the isolated gate transformers, and if the
>copper tubing is passed through a thick wall PE tubing ( polyflow(R) )
>through the interior of the toroid, very good HV standoff (perhaps
>5kV or more) could be achieved, cheaply using off the shelf stuff
>from Home Depot, Lowes, Wal-Mart, etc.

Yeah.  That would be exceptional isolation.  Im still not convinced on the 
coupling and leakage inductance of such a design, ie, need to see it myself 
to believe it.


>-------------------------------------
>Ok, imagine your circuit, but build a mirror image with bottom 4X drivers
>tied to (-) power with neutral (+).  Tie together at a terminal with two AC
>caps.  Repeat on other side of bridge.  While one diagonal pair of drivers
>are discharging (driving) the load, the opposite pair are charging the caps,
>Diagonal drivers swap, now vice versa diagonal pair is driving (in opposite
>direction) while previous discharging drivers are now charging.
>Vo-N = V*4stages *2  (+/- pk).  So if you doubled number of existing
>stages on your current design, voltage would be doubled (at load) but
>each driver would still see 4X Vin stress; but most importantly 2X the power.
>Can sketch up a drawing a Excel to clarify.  I also ran a manual switch
>simulation in Multisim and it worked no problem...  :^)

I would really like to see a drawing of this.  I just cant make it out in 
my head what you mean.  I thought i WAS using an h-bridge, but i guess not?
Please, drawing would be excellent.

I also dont understand how the drivers are seeing 4X Vin stress?  Maybe i 
need to see your scheme to understand.


> > >Another possibility is build a "voltage adder" circuit using multiples 
> of this
> > >circuit to drive a driver transformer cascade.  Imagine what could be done
> > >with 30-60kV pk going into base of resonator like a magnifier!
> >
> > Im not sure what a voltage adder is, example?
>
>Look up "Fractional Turn Transformer" in Google.  Imagine 4 large identical
>toroids. Wind 1 turn from you present driver (4 in parallel) around each 
>toroid.
>Then wind 'X' turns around _ALL_ four toroids.  Vo ~Vin * 4 * Xturns.  Dunk
>whole assembly in oil.  Now what's limiting your drive output voltage?
>This
>technique is used for linear accelerators, and Klystron drivers.  This "drive"
>transformer Vo could directly feed the base of the resonator.

This is truly insane ;-)  I DID look up fractional turn transformers and 
was blown away by the concept.  Now my question. MUST they be toroids?  OR 
would something like an oversized flyback core work? Perhaps if the gap was 
removed?  I suppose even still ive been seeing large ferrite rings on ebay 
for not too much (in sets of 4).  I really just cant imagine feeding the 
resonator so many kv!  And the fractional turn transformer makes it... 
possible!  The only thing im unsure of, is saturating the cores.  Now, if i 
was to run some math on this, would i add up the dimentions for ALL 4 (or 
however many) cores together and say there is 1/4 turn on it?  Or does it 
somehow still count as 1 full turn?  I guess i need to think about it more, 
but the idea is really something else.

Dave! why arent you building some of these ideas!  And if you have been, 
can i see?


>Steve, you are doing outstanding.  A reality check, I am very impressed 
>with your
>projects to date, and your successes with your knowledge base.  Your 
>willingness
>to try new things and "Just do it!" will serve you well in the future.  I 
>wish you
>much success in your studies and future endeavors.

Thank you very much!  You dont know how excited i get when people get 
interested in my designs (or any of my work for that matter).

Steve Ward


>Best Regards
>Dave Sharpe, TCBOR/HEAS
>Chesterfield, VA. USA
>