RE: Over-voltage at Synchronous Gap ? ? ?

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Original poster: "Mccauley, Daniel H" <daniel.h.mccauley-at-lmco-dot-com> 



Great info and simulations Kurt.  I'll definitely check them out tonite
when I get home from work.
I appreciate the effort you put together in this reply!

The Captain


 > Hi Dan,
 >
 > I did a series of 29 microsim8-pspice simulations on that. Malcolm is
 > very right, the question is: HOW MUCH LTR? My example: 15/60 NST with
 > LTR caps of 33nF, 30nF and 25nF (at line f=50Hz), and a
 > classic coil I'm
 > currently building (fairly detailed simulation). The varied
 > variable was
 > the time delay of the SRSG, relative to the zero crossing
 > voltage of the
 > 50Hz line, recording the peak voltage on the cap, the peak secondary
 > voltage and the line-power draw (a PFC capacitor of 80uF kept
 > the power
 > factor in a acceptable range, without disturbing the sim
 > otherwise). The
 > main results are as follows:
 >
 > LTRcap=33nF, Vcap.max=24.2kV(-at-5.5ms delay),
 > Vsec.max=411kV(-at-4.5ms delay)
 > LTRcap=30nF, Vcap.max=28.4kV(-at-5.5ms delay),
 > Vsec.max=453kV(-at-4.5ms delay)
 > LTRcap=25nF, Vcap.max=39.9kV(-at-5.5ms delay),
 > Vsec.max=558kV(-at-4.5ms delay)
 >
 > A summary PDF of the results can be had under
 > http://home.tiscalinet.ch/m.schraner/LTR_Sim1.pdf   (484kB)
 > ...and a more appropriate result in excel-form at
 > http://home.tiscalinet.ch/m.schraner/LTR_Simu.xls   (171kB)
 >
 > Considering maximum cap-voltage (with inductive kick), this voltage is
 > NOT identical with the SRSG time delay, obtained for max. secondary
 > voltage ( and also not identical with the firing voltage of the main
 > SRSG gap).
 > It appears, that peak primary cap voltage is quite sensitive, on how
 > much the LTR cap value deviates from the "ideal" value of 33.2nF. The
 > recommended value for 15/60 NST's, of 30nF, in the table under:
 >
 > http://hot-streamer-dot-com/temp/MMCcapSales.gif
 >
 > is just ~3nF below the "ideal" value, but brings more than 4kV more
 > stress on the cap. Thinking, 2 more 150nF caps on each of the 2 MMC
 > strings would make it "safer", in fact make it worse, because the
 > capacitance is then reduced to 25nF (instead of 33nF), which leads to
 > ~16kV more possible stress to the primary capacitor, than
 > "ideal" 33nF.
 >
 > This investigation has shown me to be careful about selecting a
 > deviating value for SRSG LTR-caps, relative to the "ideal" value (in
 > fact I decided to make an MMC of 2 x 12 150nF CD's + 1 x 12 100nF CD's
 > for my 15/60 NST). The little new coil is not yet completely
 > buildt and
 > tested, but I'll report the results.
 >
 > Cheers,  Kurt



 >  > I am having some interesting phenomenon occur at the
 > safety gap I have
 >  > at my
 >  > SRSG gap.
 >  >
 >  > If I adjust my SRSG to the point of which (should yield
 > 75% to 100% maximum
 >  > voltage at primary capacitor), i get firing of my safety gap with
 >  > loud bangs (which are likely because the MMC is
 > discharging into the safety
 >  > gap)  The safety gap is adjusted slightly larger than the
 > no-load voltage
 >  > on the NST.  I am confused to why this gap is firing as I
 > am using a LTR
 >  > type capacitor and didn't think i could get over-voltages
 > using a SRSG.
 >  >
 >  > Any thoughts??
 >  >
 >  > Specs on my small coil are:
 >  >
 >  > 15kV, 60MA NST
 >  > 0.0257uF, 24kV (MMC - LTR sized)
 >  > Standard secondary and primary coil
 >  >
 >  > The Captain
 >
 >
 >
 >
 >
 >
 >