Half-Bridge questions . . .

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Original poster: "Mccauley, Daniel H by way of Terry Fritz <teslalist-at-qwest-dot-net>" <daniel.h.mccauley-at-lmco-dot-com>


Just some half-bridge topology questions . . . as this new design i'm
working on doesn't require the full-bridge topology.


When utilizing a DC source to run a half-bridge (2 FET) the outputs would
the output connections typically be:

1.  One connection between two FETs

2.  The second connection centered between the DC+ and DC- rail of the
h-bridge with series DC blocking capacitors
on both side of this connection.

I've seen it dones many different ways, and wanted to see which worked best
for SSTC work.

Thanks

Dan