Re: SSTC, xfmr gate drive oddity

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "Jan Wagner by way of Terry Fritz <twftesla-at-qwest-dot-net>" <jwagner-at-cc.hut.fi>


> International Rectifier calls it a totem pole circuit, although they
> do put it in "quotes" ; ). See it in IR Application Note AN-940,

Hmm... odd... maybe I was wrong after all. "Totem pole" is maybe a general
name for how the schematic looks like, and not how it works?
 
> http://www.irf-dot-com/technical-info/an940/an-940p3.htm 
> There is much good info about this subject here, too.
> 
> Based on what I see in this note, there has to be a simple way to do
> it. In several of their diagrams, they show the P and N channel
> MOSFET pair inside of a single IC. Nothing really special about it,
> except that it's inside a hermetically sealed package with probably a
> million other components that support the circuit ; (

Yup, it sure looks simple. Luckily they also tell that:

"When using this gate connection, care should be exercised to have a
gate drive signal with fast rise time to minimize cross-conduction... As
shown in Figure 5, if the two gates have the same drive signal, there
is a period of time when the gate drive transitions between the lower
threshold, say 3 V, and the upper threshold , say 15-3 V=12 V, in which
both devices are on."

> It seems that the circuit would have inherent dead time, I guess, if
> the two MOSFET's were identical.

There must be some extra parts in the logic ICs, as you said.
Probably a trade secret or something...

Otherwise CD4049 and all other ICs with totem pole outputs would be
burning up all the time. Maybe it's the channel on resistances that limits
the shoot through current?
 
> If I'm understanding correctly, Robert H. suggested in a previous
> post that the MOSFET gates must be biased at 1/2Vcc in order for the
> circuit to work properly. I tried this on a breadboard, but instead
> of using fixed-value resistors I used a pot. One side went to +, the
> other went to GND, the arm (wiper) went to both gates of the N and P
> channel MOSFET pair (IRFZ20 and IRF9540). That way I could adjust the
> bias as necessary.
> 
> Results:
> 
> I couldn't get it to work well. At 1/2Vcc (halfway on pot) the
> waveform was exactly as described by Jan in the original post, with
> the square wave coming out of the MOSFET pair riding on DC bias, and
> not having much voltage swing. (~2.5V p-p)

Yeah I tried that too, but with fixed resistors. Same result as you had.

> BUT!
> 
> After adjusting the pot almost all the way toward one side, it worked
> quite well. Fairly clean GND to 12V square wave into the primary of
> the gate transformer, through a 1uF coupling cap. No load on the
> secondary winding (my xfmr is 7 turns pri, 14 turns sec, on some high
> u core). The only problem with this is, that it drew quite a bit of
> current from the signal generator (TL494) and the IC got hot. So did
> the pot.

So, the pot was almost shorting the gate drive to 12V?

Hey, maybe the two mosfets should be biased separately? The lower one at
3V and the upper one at 9V? And of course, couple in the signal with two
caps. I.e. upper one will get 9V-6V=3V to 9V+6V=15V V_gate, so V_source
follows 15V-V_t=15V-3V=12V. 

The 4 zener biasing thingie suggested by Malcolm sounds promising too... 

(ok then, two more thing to try out... desperate measures... ;)

cheers,
 - Jan

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