Re: Another SSTC Question and GATE DRIVE XFRM Design

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "rob by way of Terry Fritz <twftesla-at-qwest-dot-net>" <rob-at-pythonemproject-dot-com>

Tesla list wrote:
> 
> Original poster: "Mccauley, Daniel H by way of Terry Fritz
<twftesla-at-qwest-dot-net>" <daniel.h.mccauley-at-lmco-dot-com>
> 
>         Your gate driver transformer should be designed properly.  You
> should use a ferrite core.
> 
>         The following equations should be used to determine the number of
> turns required for optimal operation depending on material used, voltage
> swing, and frequency:
> 
>         (V/N) = A * e(dB/dt)
> 
>         where:  V is in volts
>                 N is number of turns
>                 A is cross sectional area of your core
>                 B is in Gauss
>                 t is in seconds
> 
>

You will puncture the gate before you saturate a core with a gate drive
signal.  Thus B is irrelevant. You need to be more worried about the
leakage inductance of your transformer.  You can measure it with an LCR
meter with the secondary open and shorted and then applying some
algebra.  However, the easiest way to build a good transformer is to use
the least number of turns that will give you a solid looking square wave
into a 10ohm resistor (and not cause excess dissipation in the driver). 
10ohms is just arbitrary but it works for me.  Using the highest
permeability core will ensure the least amount of turns and thus the
lowest leakage inductance.

Its the leakage inductance that causes spikes on the transitions of the
square wave.

You might wonder, why not adjust the transformer with a FET attached?  
Because the gate-source capacitance is a function of the drain-source
voltage, the FET has to be biased up.  If you have a good isolation
transformer, you may be able to measure the working gate-source waveform
with a scope.  

Rob.


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