Re: phase locked loop SSTC

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "Paul Nicholson by way of Terry Fritz <twftesla-at-qwest-dot-net>" <paul-at-abelian.demon.co.uk>

Jan Florian Wagner wrote:

> At resonance the I_sense output signal is about 40Vpp, pretty
> sufficient.  But at lower freqs it is close to nil. 

Ah, that's the problem then.  The feedback chain *must* present a 
clean square wave to the comparator throughout the tuning range, not
just near resonance.  Hence plenty of gain - a limiting amplifier
followed by a Schmitt trigger.  Furthermore this signal must come
from the secondary base current, not the drive voltage, so your
current sensor must be able to pick up just a few mA of current, at
the same time as ignoring 300V or so of square wave!

> Haven't measured Q but maybe 80 or so...

Adequate.  Higher Q would increase your problems right now.

> Phase could be discarded by using...

No!  It's the feedback signal amplitude which must be discarded - the
phase you want to keep.

You should be able to manually tune the vco across its range, open-
loop, and see a clean square wave coming back to the comparator at
all times.  The edges of the feedback signal should be almost 90 deg
ahead of the vco signal below fres, and 90 deg behind the vco when
above fres.  Without this condition, the PLL will not lock without
some manual fiddling, will only remain in lock if Fres doesn't jump,
and performance will be poor.  

In this way, at the instant of first closing the loop, the feedback
signal, the comparator output, and the vco output signal, are all
random square waves - ie broadband noise out of the vco, from which
the secondary filters out current at its Fres, which then appears at
the comparator feedback,  and in a very short period of time (a cycle
or two), the broadband noise from the vco contracts down to a single
steady frequency.

> Manual tuning yeilds much better results. :o(

Yes, then your PLL is not doing its job.  I don't think you need
any fancy vco or comparator - the most effort needs to go into the
current sensor to make it ignore V, and to make sure the sensitivity
to I is sufficient throughout the range.

The major problem I foresee with PLL control of the SSTC oscillator,
is the presence of the unloaded 1/2 wave resonance. The phase change
(of I wrt V) on passing through this frequency would drive the vco
to the top of its range.  Thus the upper vco limit must be set
below this frequency, thereby preventing the vco tracking up to the
somewhat higher *loaded* 1/2 wave during ground arcs.  So I think a
'simple' PLL should work very well as long as you're generating
corona, brush discharges to air, etc, in which the load never falls
below the secondary characteristic impedance.  I think you should
focus on getting a solid (automatic) lock over the 20% or so tuning
range needed for this, using a simple vco/pll and concentrating your
effort on the current sensor and shielding of the feedback chain.

Another problem, is that the vco could easily lock to a sub-harmonic,
eg 1/3rd of the 3/4 wave overtone. The vco would be within it's
'legal' tuning range, and the feedback edges would have the right
phase to induce lock.  Eg in the example 
 http://www.abelian.demon.co.uk/tssp/tmp/pn1ld.unloaded.gif
this would occur at 355/3 kHz - quite close to the 140kHz Fres.

I've been playing with adding distributed C to try to shift the
3/4 mode out of harms way, but with coupling transformers adding in
their own self-resonances, the whole thing is getting too
complicated and delicate.

Perhaps the only hope of getting around these very nasty problems
is some sort of 'intelligent' circuit, with the RF signal generated
by a tame microprocessor.  A sort of 'engine management system' for
SSTCs!  Then it becomes a nice programming problem.

--
Paul Nicholson,
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