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Re: phase locked loop SSTC



Original poster: "Jan Florian Wagner by way of Terry Fritz <twftesla-at-qwest-dot-net>" <jwagner-at-cc.hut.fi>


> > Can't set it above f_res more than 10-20kHz. The problem is with a
> > high Q coil it looks like the PLL lands either on the lowest or
> > highest freq in a "bad case", because there's no proper signal
> > from the current sense.
> You'll have to ensure that the feedback signal is present at a
> sufficient level to lock, throughout the vco tuning range.  You 
> only need phase, not amplitude, so a limiting amplifier before
> the phase comparator might be called for.

At resonance the I_sense output signal is about 40Vpp, pretty sufficient.
But at lower freqs it is close to nil. So a narrow PLL freq range is
necessary. Haven't measured Q but maybe 80 or so...

Phase could be discarded by using one PLL to "demodulate" the TC
resonant frequency and feed the "demodulated" signal to the VCO of a 
CD4046 with identical timing components. Less problems. maybe. Haven't
tried yet.

Manual tuning yeilds much better results. :o(

> Ok, that means your PLL is not making the jump.  Hence weedy
> performance into the arc.  You've set an upper limit on the vco which
> prevents the necessary tracking, in order to get stable operation
> before arc.  I think you need to experiment to get a good wide,
> reliable locking range - and then tell us all how to do it!!

hmm I might try but actually I just got an idea with PIC16F84, two or
three comparators, a 50-500kHz square wave VCO, LCD panel and pushbuttons.
Should be a menu controlled hi-tech solid state TC. Let's see how it
goes...

> > - with ground strikes the secondary jumps to the second harmonic!!
> > very odd.  
> Not strange at all.  Arc to ground from the topload makes a
> fundamental change in the configuration of the resonator.  The

oops, yes, you're absolutely correct! Should've know it myself, but brains
didn't make *click*... :o)

> Necessary to get the full power out of your driver.  Too low Zsec
> and you reach limiting current before the variac gets to the top.
> Too high Zsec and you reach the top of the variac before limiting
> current.  Either way the VI product is less than your driver is
> capable of delivering.  I think your web page already describes
> this. 

Well, yes. I guess this is a matter of habit - I don't use current
limiting schemes at all because I guess transistors die either from
overcurrent or alternatively from high voltage spikes because turning off
durning high overcurrent (why use snubbers - they just add complexity!
;o). Squeezing out the last drops of power and mosfets on the verge of
failing isn't what I want/can do because I've too small a budget for
that... :o) "starving student"

many thanks!
 - Jan

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