Re: phase locked loop SSTC

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "Paul Nicholson by way of Terry Fritz <twftesla-at-qwest-dot-net>" <paul-at-abelian.demon.co.uk>

Jim wrote:

> If you want to do a PLL at the operating frequency, you'd
> probably need to sample at, say, 100 times the fundamental
> frequency: 100 kHz times 100 is 10MHz sample rate

Yes, but we don't to synthesise analogue samples, just a two-level
digital drive signal. Same for the input. The uP doesn't need to
compute and deliver 100 samples per cycle to a D/A output port, it
just has to toggle a bit on a port.  It'd spend most of its time
looping and counting, looking for a state change on the base current
sensor bit. Merely 100 uP instructions per cycle would be fine,
rather than 100 computations. So a 10Mhz or 20Mhz clock rate would be
great for a start.

Jan wrote:
> But maybe a laptop PC with >300MHz and fast parallel port could
> stand this task

You're a genius.  Of course it will!  The parallel port will do
nicely for trying out the control algorithms while hooked up to a
low voltage prototype circuit.

> Yes, the frequencies are the same. But, the duty cycles aren't! 
> The uC output is 50% always.
> But if the TC sec is driven at a freq somewhere around resonant,
> the signal derived from the base current (amplfied,clipped=>square
> wave) will not be 50%. 

Eh?  Why ever not?  The clipped base current feedback signal should
be jolly close to 50%.  Something sounds wrong.

> An off the shelve always-in-tune SSTC driver certainly would have
> its benefits.

Right!  And I can't see the catch yet.
--
Paul Nicholson
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