IR 1/2 bridge driver - Rev 01

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Original poster: "David Sharpe by way of Terry Fritz <twftesla-at-qwest-dot-net>" <sccr4us-at-erols-dot-com>

All
In reviewing schematic last night, I found multiple errors... $^C
I'm sorry but trying to broadcast info as quickly as it becomes
available to Tesla Community.
1.  In Staccato Modulator, the timing capacitor for the
      staccato astable oscillator is missing, it should be between
      the lower antiparallel diodes and 'COM' connection
      of TLC555 (A36:B38 region of spreadsheet).
2.  The values around the monostable gives the PW/Fo
      shown.  I will redetermine and provide appropriate
      capacitor value that gives these signals later this
      week.
      The staccato modulator was simulated successfully
      in both Multisim V2001 and EWB.  I'm contemplating
      adjusting PW and Fo size to 1Meg and modify
      capacitor sizing to allow lower modulation
      frequency/wider adjustment range. Having a switched
      capacitor allowing up to several Khz modulation
      frequencies is also possible.
      Remote shutdown with OVP, OCP or hard fault is
      easily implemented by pulling Ct of IR chip to chip COM,
      or alternately, placing a 100K pull up on pin 4 of TLC555
      and pulling pin 4 of astable to COM.
3.  A GS/GE TVSS should be installed across devices and
      is not shown on schematic, I would recommend a 15V
      bidirectional device.  68 ohm VGE is a shot in the dark
      100 ohm may perform better and reduce switch ringing.
3.  I'm working on a more detailed half-brdge model
      spreadsheet, based on Fairchild AN9012.  The currents
      given in schematic are listed as Itank, but in reality are
      "line currents with raw full wave rectified DC" (but
      LP filtering to prevent conducted EMI in place).
      Explanation and derivation is given in AN.  This is
      directly applicable to a raw rectified DC SSTC or
      Induction Heating application.

Also note that with a half bridge; the voltage across the
resonant load is half the applied VDC, but the current
is doubled (for same power input) versus a full bridge
converter.  So to gain a power advantage with a
simpler half bridge, one must use the highest voltage
possible, consistent with power device reliability,
and carefully monitor peak currents and device heating.

Another extension of this circuit is use an additional IR
driver and IGBT/FET output totem pole.  Invert LO
output of first driver (master) and feed into Ct terminal
of second chip (slave).  How about a full bridge
capable of easily 2kW of power with a total active
silicon cost of <$35.00?

Again, sorry for any confusion concerning this
circuit.

Best Regards
Dave Sharpe, TCBOR
Chesterfield, VA. USA