[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: SSTC probs



Original poster: "by way of Terry Fritz <twftesla-at-qwest-dot-net>" <cwillis-at-guilford.edu>


Hey Matt,

I think you are using a single transistor, right?  In this case you are
most likely seeing a flyback voltage of 2-3 times the drain supply voltage
when the transistor is off.  See the waveforms at my website,
www.angelfire-dot-com/electronic/cwillis/sstc.html.  There is no path in your
setup (I am guessing) for any current to flow "out" of the primary when the
FET is off, and the voltage at the drain during this time is not "clamped"
to the supply if it is higher than the drain supply rail voltage.  A
half-bridge circuit is much much better for high-power FET coils.  See
either my new design, or www.richieburnett.co.uk or www.alansharp.co.uk for
more info on this configuration.  Your single-FET design will be fine if
you allow for 3 times the drain supply voltage when you select the FET, and
for small FET coils operated from a low-VDC supply should be fine using
only one.
-Carl