Re: Paralleling FET's

Bryan's strategy would be important if you were running your FETs as a
linear amplifier, as opposed to a switch. In most TC power oscillator
applications, the FET is a switch, so all you worry about is making sure
that they turn on and off at mostly the same time, and even this is non

A FET is a voltage controlled current source.  So let's look at what
happens to a set of paralleled FETs as they turn on.  You put a healthy
bias on all the gates (more than enough to turn them on, say 10V). The gate
capacitances start to charge and the FET's start to turn on, all at
different rates. As each one starts to turn on, current flows through it up
to the amount of current determined by the Rds on characteristics. Each
device is essentially independent of its siblings. The power dissipation is
mostly determined by Rds on and the Vds. If one device has a lower Rds,
more current will flow, but, you don't get the thermal runaway
characteristic of bipolar devices, where as it gets hotter, the current
increases, etc.

And recall, once the FET is on, there isn't any current flowing in the gate
(the Cgs capacitance is all charged up), so a series resistor driven from a
constant voltage source makes no difference.

So, it sort of depends on the FET, but you don't need to worry too much
about paralleling.  In any case, changing the series gate resistor isn't
going to make a heck of a lot of difference, because the FET has a very
high input impedance (many Meg).  There IS a concern about the fairly high
gate capacitance, which charges more or less slowly depending on its
magnitude, and appears orders of magnitude larger than the specsheet value
of Cgs due to the "Miller effect".  I would expect, though, that for FETS
of the same type, that the device parameters would be more closely matched
than the resistors you might be using, especially over temperature

Even though FETs have a very high input impedance (they are basically a
voltage controlled device) and don't require much gate power, the key is to
drive them from a very low impedance source that can source and sink a lot
of current so you charge and discharge that gate capacitance quickly. You
need enough drive curernt to turn those babies on in a few tens or hundreds
of nanoseconds. A simple common emitter BJT driver stage typically won't
work very well (discharges fast, but charging is limited by the collector
resistor). I'd suggest one of the many cheap FET driver chips from such
mfrs as Allegro or IR. They have a pair of transistors in a totempole or
complementary symmetry arrangement which can both source and sink.  

Once the paralleled FETs are all turned on, they will parallel nicely
(unlike BJT's which require emitter ballasting resistors to properly
current share).

I WOULD but ferrite beads on the gate leads though, and check for spurious
oscillation.  Paralleled FET circuits seem to be more prone to oscillation,
because the high "switched output" couples back into the gate.  Power FETs
have signficant gain way up into the 100 MHz range, and oscillation could
dramatically increase the dissipation of a fairly low loss switching
circuit (the FETs really only dissipate power when they are changing state,
and oscillation makes them do that a lot more).

> From: Tesla List <tesla-at-pupman-dot-com>
> To: tesla-at-pupman-dot-com
> Subject: Paralleling FET's
> Date: Saturday, October 16, 1999 10:29 PM
> Original Poster: Bryan St <warp27-at-juno-dot-com> 
> Steve
> To put FET's in parallel, you have to find out each one's turn on
> information exactly.  Then you have to put equalizing resistors in the
> gate so that they all turn on at the _same_ time and the _same_ amount. 
> If you don't, you get to watch the casing fly right off one of the little
> buggers when they hog the power.  I am not sure what the value range of
> resistor you will be needing.  To find the individual turn on info, you
> will need your multimeter, a wrap around circuit and a paper and pencil
> to record stuff.  Basically, your wrap around circuit has a load resistor
> on the source or drain.  You have a few resistors and a switch so you can
> select the one in the gate.  You set your multimeter up to measure
> current through the FET. You put a controlled voltage that _must_ remain
> constant during your testing.  You measure the current flowing through
> your FET with a medium-sized resistor.  Then you write down this value. 
> Put the next FET in.  Change the gate resistor until the current through
> your 2nd FET is as close to the first as possible.  Then take the next
> FET and so on.  You might want to test a few before you try equalizing to
> make sure you get a current value that is in the median of the other's.
> EE's:  If I made a mistake please correct me.
> Bryan
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