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Gap Dwell



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Hi Group,
I'll probably get slack for this, but here goes anyway.
I have done a simple spice model of my TC in progress. Attached are two
pictures, one of the circuit (schqnch2.jpg), the other of the waveforms of
the primary/secondary voltage (quench2.jpg). I believe this shows the dwell
times you guys are talking about where the primary mins and the secondary
maxs.
Again this is very simplistic/theoretical since arcing is impossible to
simulate and other parasitic elements are not included.
If the pictures don't come through look for... 
http://d0server1.fnal.gov/www/huffhtml/tesla/schqnch1.jpg k=0.1
http://d0server1.fnal.gov/www/huffhtml/tesla/quench1.jpg k=0.1
http://d0server1.fnal.gov/www/huffhtml/tesla/schqnch2.jpg k=0.2
http://d0server1.fnal.gov/www/huffhtml/tesla/quench2.jpg k=0.2
dave

[ Note: The pictures will come to those who are on the "image/large file
list" -- chip]