Original poster: "Gerry Reynolds" <gerryreynolds@xxxxxxxxxxxxx> Hi Aaron,I'll through out some thoughts. If the SG has fired, and the gate drive is at the voltage generated by the TVS, there may be a problem with Vce drop across each of the IGBT's. Dont know what the saturation voltage is for each one, but the bottom IGBT would get the most gate drive and the top IGBT would see the smallest gate drive since its emitter voltage would be the accumlative sum of Vce from all the IGBT's below it.
If the SG is OFF, each emitter of the IGBT would be at a different voltage whereas the gate voltage would be at the emitter voltage of the bottom IGBT. All the other IGBT's above it will see a gate voltage negative relative to its emitter voltage and the top IGBT will see a negative gate voltage as large as the SG breakdown voltage. I dont think these parts will survive this.
Gerry R.
Original poster: "J. Aaron Holmes" <jaholmes@xxxxxxxxxxxxxxxxxx> No comments? In case there was any trouble visualizing this (I doubt it, but...), here's a sketch done using top-of-the-line schematic-drawing software: mspaint.exe ;-) http://silicon-arcana.com/SG-SiSG.jpg