Re: SSSSTC Coil questions for Mr. Steve

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "Steven Ward" <srward16-at-hotmail-dot-com> 

Hi Dave, i will try to answer your questions:


>------------------------------
>I suspect the delays are from your cascaded GDT's.

Cascaded?  I think you may have misunderstood my driving scheme.  In the 
schematic i have a TC442X pair driving a small GDT.  This drives 1 
half-bridge (which makes up one beefy gate driver).  This half-bridge ALONE 
drives ALL 16 mosfets.  There is one large GDT per each 4 fets. So 4 gate 
drivers, all of their primaries connect to that half-bridge.  There is no 
cascading of GDTs.



  Maybe a high
>power
>current loop with indiividual I>V converter transformers at each switch
>pair may reduce delays and losses.

If i knew more about electronics i would be able to follow you... to tell 
you the truth, im a freshmen in college and havent take a single course in 
electronics yet.  I *THINK* i understand what your saying, but im not sure 
how to design/implement this.

  I would also look at possibly
>combining
>stages in next attempt, as example, IDK if you really need the 74LS14
>inverters, you may have enough drive from LT016 to direct drive the
>TC4420's.

This is correct, im going to pull the 74hc14 out of there, its adding like 
60ns total that is not needed.  I used it to ensure noise protection, but 
its really not needed.  Its all built on a breadboard right now so this is 
an easy change.



>I need a litle more detail with your GDT configuration, (core, number of 
>turns),
>I assume you are using one per FET totem pole, with 4 primaries paralleled
>to master driver?

The cores are (if i can remember!) F-114A-77.  They are type 77 material 
with a U of 2000.  I think im using 11 turns on the transformers.  I have 5 
windings on each core, 4 of the windings are driving 4 fets (or 2 of the 
half-bridges) and 1 primary going to the half-bridge gate driver mentioned 
above.

>Perform a little calculus and determine where the 2nd derivative (most rapid)
>slope change is.  I agree with you, you are probably at diminishing 
>returns with
>4-5 stages (8-10X Vin multiplication).  Another idea struck me with this
>design, you might be able to turn this topology into a full bridge and double
>applied voltage again.  Need to think about it a little more...   :^?

Umm, start calculus this semester soo...

anyway, this IS a full bridge!  If you look at my page im using two 4 level 
inverters and are running oppositely of eachother.  Its effectively a full 
bridge to the best of my knowledge.  I basically did this because normally, 
the output of a single inverter would go through a DC blocking cap- through 
a load- then back to ground/neutral.  I didnt like the idea of that, so i 
built another inverter to go on the other side of the load.

>Another possibility is build a "voltage adder" circuit using multiples of this
>circuit to drive a driver transformer cascade.  Imagine what could be done
>with 30-60kV pk going into base of resonator like a magnifier!

Im not sure what a voltage adder is, example?

30-60kv base drive sure would allow for some massive powers to be pushed 
into the resonator, but this sounds like a daunting feat.

Dave, I hope we are starting to get clear with eachother on this topic.  My 
limited knowledge doesnt help things, but im trying ;-)

Steve