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Re: 10+MHz SSTC Gate Drive Circuit Finalized



Original poster: Kchdlh-at-aol-dot-com 

Dan (& all)-

The 10-90% rise/fall times of the original driving pulse is ~9 ns, Tr of 
the output is ~250 ns and Tf of the output is ~200 ns.  But looking at the 
plus-going edges of the secondary voltages, I see ~3 cycles of oscillation 
so some damping would be needed, at least in this simulation.  I chose the 
27 ohms and the k=0.9 just for starters merely to prove out my basic idea 
for eliminating pulse-overlap.  Same for the 5n capacitive loads: they're 
nowhere near MOSFETs, clearly.  Anyone wanting to try this circuit would 
have to tweak it in the real world!

Changing the transformer's k to 0.99 does not improve the Tr & Tf but that 
oscillation increases.  The osc. is damped by putting 150 ohms across each 
secondary.

In a real circuit, one should be able to do a lot better, using this 
circuit,  than those simulated Tr & Tf times.

In your circuit, I'd still worry about zenering the NPNs.  It seems you 
could put diodes in series with the emitters to avoid that, giving up 0.7 V 
of drive.

Ken Herrick
<mailto:kchdlh-at-juno-dot-com>kchdlh-at-juno-dot-com

In a message dated 9/20/03 9:14:29 PM Pacific Daylight Time, 
tesla-at-pupman-dot-com writes:
Original poster: dhmccauley-at-spacecatlighting-dot-com


Ken,

I have a few comments and questions.

1.  What kind of rise-times are you getting on your ON pulses?  I can't tell
too well by your plots, but they do appear to look kind of long (>100ns?)
especially considering
such a small MOSFET load and only a 10V On-Pulse.

2.  The output impedance of your pulse source seems kind of hi (27 ohms?)
Typically MOSFET drivers (either packaged, or built discretely) are usually
less than 1 ohm.

3.  Your gate transformer seems to have too much leakage inductance (low
k=0.9)  Almost every gate transformer I've ever built or purchased
commercially typically
has k values of 0.9990 or greater.

4.  It seems you are trying to be as detailed as possible with this
simulation and with the results you get.  If you really want to be this
detailed, you need to create a better
model for the MOSFET gate.  Using just a single capacitor is a poor model
for a gate load.  There are actually three primary capacitances (Gate, G-D,
G-S), all of them
acting non-linear, which need to be accounted for.

5.  For low frequency work (<300kHz), you'll find out that you really don't
need something too elaborate.  I just finished simulating, building, and
testing my new 15kW SSTC
Gate Drive circuit which will be switching (2) IXFN44N50 FETs in parallel
per leg of the full-bridge at about 150kHz.  (Thats approximately 45nF
between the two gates)
After building my gate transformer, simulating it, and then testing it with
the actual FETs, I found all i need is a 1.2 ohm resistor in series with the
gates for almost a perfect
gate signal.  I did get some ringing and overshoots, but with a zener
clamping circuit (bi-directional), this dampens the ringing, clamps the
overshoot, and provides almost
a perfectly square waveform at 150kHz with risetimes less than 100nS.

Dan




 > I'll prevail on Terry to put up
 > http://hot-streamer-dot-com/temp/ssdrvr-kch5.pdf and
 > http://hot-streamer-dot-com/temp/ssdrvr-kch6.pdf.  These show the schematic
 > and simulation-waveforms of a s.s.-driver circuit that I think solves the
 > problem of drive-signal overlap.
 >
 > TX1 drives 2 identical circuits that are shown grounded merely for
 > convenience of the simulation.  In the top one...
 >
 > 1.  Initial positive & negative excursions charge up C3 and C2, thus
 > keeping transformer loading symmetrical.  The  capacitors are charged
 > through the forward-biased b:c junctions of Q1 or Q2.  When not so acting
 > as charging-diodes, the transistors act as emitter followers to supply
 > the output signals.
 >
 > 2.  The circuit of D2, D1 and Q6 is what prevents signal overlap.  For
 > negative TX1 excursions, D1 conducts, bypassing D2 and Q6.  But for
 > positive excursions, the D2/Q6 branch remains non-conducting until TX1's
 > voltage becomes ~1.4 V more positive than the voltage on C3.  At that
 > point, Q6 turns on, pulling Q1's emitter to TX1's + voltage less ~1.4 V.
 >
 > 3.  By transformer action between the secondaries, at the instant Q6
 > starts to turn on, the Q3/Q4 output (in the lower circuit) must have
 > reached essentially 0 V.  The waveforms bear this out.  There is no
 > occasion when both outputs are positive at the same time except for the
 > very first transition after turn-on, when they are very briefly both
 > ~+1.5 V.
 >
 > 4.  The unconventional connection of the return-sides of the output
 > signals establish the output baselines at 0 V.
 >
 > 5.  R3 ensures that the capacitors start out with 0 V (in the real
 > circuit); R3 & R5 may not be necessary.
 >
 > 6.  Pull-down resistors may be wanted should the drive circuits be
 > disconnectable from MOSFETs; the circuit works fine (in simulation, of
 > course!) with 4.7Ks.
 >
 > This may very well solve my own problem; time will, I hope, tell.
 >
 > Ken Herrick
 >
 >
 >
 >
 >