An SSTC simulation

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "K. C. Herrick" <kchdlh-at-juno-dot-com> 

Here's some food-for-thought for other SSTC nuts.  See simulation
schematic http://hot-streamer-dot-com/temp/tcl-basic.pdf and waveforms
http://hot-streamer-dot-com/temp/tcl-basicA.pdf,
http://hot-streamer-dot-com/temp/tcl-basicB.pdf  and
http://hot-streamer-dot-com/temp/tcl-basicC.pdf.  What I propose,
 >basically<, is to resonantly charge a pair of capacitances directly from
the mains, one charged on each positive half-cycle and the other on each
negative and then, at the end of each full mains cycle, fully discharge
the capacitances alternately at Fr, into the primary of the Tesla coil.
"Fr" is the resonant frequency of a broadly-series-resonant primary
loosely coupled (as is resultant in a Tesla coil) to the conventional
parallel-tuned secondary.  Oscillation at Fr is to be maintained in a
closed-loop feedback circuit encompassing primary and secondary (and
generally in the scheme I have already employed successfully).  I take
note of Terry Fritz's work in that I propose using multiple
switching-transistors and multiple primary-resonating capacitors,
effectively paralleled at Fr.

In the schematic...

Six pairs of 100 uF storage capacitors, represented by C4/R18 and C7/R19,
are resonantly charged, with TX3, directly from the 115 VAC mains.  Each
capacitor is charged through the protective diode of the power-MOSFET
circuit that is in series with it (D10/D11/D20 and D9/D12/D16 in the
schematic); serendipitously, no other mains-rectifiers are required.
S1/R20 and S2/R21, together with the pairs of capacitors at the switch
inputs, simulate the MOSFETs.  The MOSFET/series-capacitor circuit is
essentially that which I have already used in my earlier sstc.  In that
circuit, each protective diode acts to clamp the opposite MOSFET's
off-voltage to about twice the storage-capacitor voltage.  During the
spark event, the MOSFETs do see an additional off-voltage due to Fr
current through the capacitors' ESRs, but in this simulation the peaks do
not exceed 600 V.  In the real circuit, each MOSFET will have a Shottky
diode in series, with the protective diode across the pair (and in the
real circuit I would likely have to use 800 V MOSFETs).

Take note that, in the simulation schematic, I have had to string some
diodes in series due to model-limitations.

To effect the loop-feedback, a small 90-degree-shifted reference voltage
is taken from the secondary's return circuit, across C13.  That is
amplified and then phase-controlled (by EX-OR U4) so that the correct
feedback-phase exists only during the negative mains half-cycles.  That
is to allow a full mains cycle to occur following each spark event so
that both storage-capacitor groups may become recharged on alternate
half-cycles.  The reference voltage is further amplified for excitation
of 3 dual driver/crossover-control circuits (that I have previously
described on the List; correction to the circuit, here, consists of the
addition of D13, D15, D14 & D17, the relocation of R12 and R13 and the
addition of C17 and C18).

Each of the 3 driver/crossover circuits is to drive 2 pairs of power
MOSFETs; for simulation, the 6 MOSFET pairs are lumped together since my
freebie simulation program will not accomodate so many analog nodes.
Each pair of MOSFETs and its associated C8/R22 element drives the 3-turn
coil primary, broadly resonating it at the approximate secondary Fr.  In
practice, I may utilize 6 mutually-closely-coupled primaries for
convenience in laying out the 6 driver groups.

This works like a champ in the simulation.  Each 120/s voltage-excursion
at U4's input shock-excites the secondary.  For each such negative-going
excursion, the shock-excitation is fed back in-phase so as to become
built up right after mains zero-crossing; for the positive-going
excursions only a minimal secondary-output is generated.  The 230 KV
maximum is reached in about 10 cycles (see waveform B) and the resultant
Fr oscillation fully discharges the storage capacitors in around 1.5 ms.
The rate of rise would, of course, be improved should any of the various
m-ohm loop resistances be amenable to reduction.

Waveform A shows two half-cycles of mains current followed by the full
secondary-voltage waveform.  Of course, the latter is shown as if no
spark occurred.  Waveform C shows the pair of drives to the
MOSFET-simulating switches; note the crossover control provided.

I hope to press forward on this; I already have the secondary (2,
12"-diameter ones, in fact), the intermediate amplifier, the pre-driver
and one driver/crossover circuit--and I've proved out the MOSFET circuit
in practice.  But regardless, perhaps some other sstc nut will be
interested in taking it on as well.  I'll be happy to email the
simulation-file to anyone else who has SIMetrix.

A crucial question in this kind of scheme is--what kind of storage
capacitors to use?  They have to be a) of relatively high capacitance and
b) capable of withstanding repeated and prolonged full charge and
discharge at 60/s.  Photoflash capacitors, likely--well under-stressed,
but it's still a tall order.

So..-dot-comments, anyone?

Ken Herrick